DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed December 6, 2024.
Claims 1-20 are pending. Claims 1, 12 and 18 are independent.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Europe on December 8, 2023. It is noted, however, that applicant has not filed a certified copy of the EP23215118.3 application as required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on December 6, 2024. This IDS has been considered.
Examiner Note
The present application has used the limitation of “first axis, second axis, third axis.” The examiner notes that typical 3D construction has word lines across the top of a structure in an X or Y direction, has vias in the periphery which penetrate in the Z direction to the appropriate “step” or plane of memory, and then extends in an X or Y direction to include multiple memory cells within the memory array proper. Thus, typical word lines, unless further limited to include connections between memory cell, can comprise coupled structured in all three dimensions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kajigaya (U.S. 2013/0070506).
Regarding independent claim 1, Kajigaya discloses a dynamic random access memory, DRAM (see page 2, par. 0036), comprising:
a block comprising a 3D array of memory cells (Fig. 2);
the block comprises a set of planes stacked along a first axis, wherein the set of planes comprises a subset of consecutively stacked planes (Fig. 2: L0-L8),
each plane of the subset of planes comprises a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis (Fig. 2: MCs), and
wherein the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane of the subset of planes (Fig. 2: SGs);
a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to one memory cells in each plane of the subset of planes (Fig. 2: LBLs);
a plurality of global bit lines (Fig. 2: GBLs), wherein the global bit lines are connected to the bit lines in each sub-block (Fig. 2: GBLs are connected to the LBLs);
a plurality of bit line selector (BLS) transistors, wherein each BLS transistor is configured to connect one of the bit lines to one of the global bit lines (Fig. 2: STs connected to LBLs and connected to GBLs through LSAs); and
a plurality of bit line pre-charge (BLP) transistors, wherein each BLP transistor is configured to connect one of the bit lines to one of a plurality of charging lines (Fig. 8: charging lines connected to ground) in order to charge the bit line (Fig. 8: PTs, see also page 5, par. 0061).
Regarding claim 2, Kajigaya discloses wherein one plane of the set of planes comprises a 2D array of BLS transistors (Fig. 2: STs).
Regarding claim 3, Kajigaya discloses wherein one plane of the set of planes comprises a 2D array of BLP transistors (Fig. 8: PTs).
Regarding claim 4, Kajigaya discloses wherein one plane of the set of planes comprises a 2D array of BLP transistors(Fig. 8: PTs);
the plane that includes the 2D array of BLP transistors is arranged on the subset of planes, wherein each BLP transistor is associated with one of the bit lines (Fig. 8: PTs are associated with LBLs); and
the plane that includes the 2D array of BLS transistors is arranged on the plane that includes the 2D array of BLP transistors, wherein each BLS transistor is associated with one of the bit lines (Fig. 8: STs are associated with LBLs).
Regarding claim 5, Kajigaya discloses wherein each BLS transistor has two terminals, and wherein each BLS transistor is connected with one of the two terminals to one of the global bit lines (Fig. 8: STs comprises two terminals and one terminal is electrically connected to GBL through Q4) and is connected with a gate of the BLS transistor to one of a plurality of select lines (Fig. 8: the gate of the STs are connected to SLs).
Regarding claim 6, Kajigaya discloses wherein each BLP transistor has two terminals, and wherein each BLP transistor is connected with one of the two terminals to one of the charging lines (Fig. 8: PTs transistors comprises two terminals and one terminal of connected to lines that goes to ground) and is connected with a gate of the BLP transistor to one of a plurality of second select lines (Fig. 8: the gate of the PTs are connected to PCs).
Regarding claim 7, Kajigaya discloses a plurality of sense amplifiers, wherein each sense amplifier is connected to one of the global bit lines (Fig. 2: LSAs connected to GBLs).
Regarding claim 8, Kajigaya discloses wherein each global bit line extends along the third axis, is associated with one respective sub-block, and is connected to a respective group of bit lines in the respective sub-block (Fig. 2: GBLs are associated with each SG and is connected to a group of LBL in each SG).
Regarding claim 9, Kajigaya discloses a plurality of word lines, wherein each word line extends in one of the planes along the second axis and is connected to one memory cell in each sub-block (Fig. 2: WLs).
Regarding claim 10, Kajigaya discloses a single word line driver shared among the word lines (Fig. 1: 18) or multiple word line drivers each shared among the word lines of the same plane; and
one or more word line selectors is configured to selectively connect the one or more word line drivers to the word lines (Fig. 1: 11).
Regarding claim 11, Kajigaya discloses a single word line selector shared among the word lines (Fig. 1: 18); or
multiple word line selectors, wherein each word line selector is shared among the word lines of the same plane,
wherein the one or more word line selectors (Fig. 1: 18) are configured to selectively connect an output of an address decoder (Fig. 1: 13) to a plurality of word line drivers (Fig. 1: 11), and
wherein the plurality of word line drivers are connected to the plurality of word lines (Fig. 1: 11 is connected to WLs).
Regarding independent claim 12, Kajigaya discloses a method for processing a dynamic random access memory, DRAM (see page 2, par. 0036), the method comprising:
forming a block comprising a 3D array of memory cells (Fig. 2), wherein
the block comprises a set of planes stacked along a first axis (Fig. 2: L0-L8),
the set of planes comprises a subset of consecutively stacked planes (Fig. 2: L0-L8),
each plane of the subset of planes comprises a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and the second axis (Fig. 2: MCs), and
the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane of the subset of planes (Fig. 2: SGs);
forming a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to one memory cell in each plane of the subset of planes (Fig. 2: LBLs);
forming a plurality of global bit lines (Fig. 2: GBLs), wherein one or more of the global bit lines are connected to the bit lines in each sub-block (Fig. 2: GBLs are connected to the LBLs);
forming a plurality of bit line selector, BLS, transistors, wherein each BLS transistor is configured to connect one of the bit lines to one of the global bit lines (Fig. 2: STs connected to LBLs and connected to GBLs through LSAs); and
forming a plurality of bit line pre-charge, BLP, transistors, wherein each BLP transistor is configured to connect one of the bit lines to one of a plurality of charging lines (Fig. 8: charging lines connected to ground) in order to charge the bit line (Fig. 8: PTs, see also page 5, par. 0061).
Regarding claim 13, Kajigaya discloses wherein a 2D array of BLS transistors is formed in one of the planes of the set of planes (Fig. 2: STs).
Regarding claim 14, Kajigaya discloses wherein a 2D array of BLP transistors is formed in another plane of the set of planes (Fig. 8: PTs).
Regarding independent claim 18, Kajigaya discloses a method for operating a dynamic random access memory (see page 2, par. 0036), DRAM:
providing the DRAM including:
a block comprising a 3D array of memory cells (Fig. 2), wherein
the block comprises a set of planes stacked along a first axis, wherein the set of planes comprises a subset of consecutively stacked planes (Fig. 2: L0-L8),
each plane of the subset of planes comprises a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis (Fig. 2: MCs), and
the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane of the subset of planes (Fig. 2: SGs);
a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to one memory cell in each plane of the subset of planes (Fig. 2: LBLs);
a plurality of global bit lines (Fig. 2: GBLs), wherein one or more of the global bit lines are connected to the bit lines in each sub-block (Fig. 2: GBLs are connected to the LBLs);
a plurality of bit line selector (BLS) transistors, wherein each BLS transistor is configured to connect one of the bit lines to one of the global bit lines (Fig. 2: STs connected to LBLs and connected to GBLs through LSAs); and
a plurality of bit line pre-charge (BLP) transistors, wherein each BLP transistor is configured to connect one of the bit lines to one of a plurality of charging lines (Fig. 8: charging lines connected to ground) in order to charge the bit line (Fig. 8: PTs, see also page 5, par. 0061);
selecting a bit line by activating the BLS transistor associated with the bit line (Fig. 8: STs), so as to connect the bit line to an associated global bit line (Fig. 8: when SL is applied, LBL is connected to GBL through LSA);
pre-charging the bit line by activating the BLP transistor associated with the bit line, so as to connect the bit line to the associated charging line (Fig. 8: PT, see page 5, par. 0061); and
sensing a charge on the associated global bit line that is connected via the BLS transistor to the bit line or providing a charge on the global bit line (see page 4, par. 0051).
Regarding claim 19, Kajigaya discloses driving a word line of the DRAM to activate a memory cell connected to the bit line to transfer data stored in a capacitor of the memory cell between the memory cell and the bit line (see page 3, par. 0045).
Regarding claim 20, Kajigaya discloses wherein the word line is driven before, after, or at the same time as selecting and pre-charging the bit line (see page 5, par. 0061).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kajigaya (U.S. 2013/0070506) in view of Nagata (U.S. 2012/0250437).
Regarding claim 15, Kajigaya discloses the limitations with respect to claim 13.
Kajigaya teaches forming the 2D array of BLS transistors (Fig. 2: STs) or the 2D array of BLP transistors (Fig. 8: PTs).
However, Kajigaya is silent with respect to forming a 2D array of dummy memory cells in the one of the planes, and wherein each dummy memory cell comprises a transistor connected to a capacitor at one or two terminals of the transistor.
Similar to Kajigaya, Nagata teaches a method for processing a dynamic random access memory (see page 1, par. 0009).
Furthermore, Nagata teaches a 2D array of dummy memory cells in the one of the planes, and wherein each dummy memory cell comprises a transistor connected to a capacitor at one or two terminals of the transistor (see Fig. 3 redundant region).
Since Nagata and Kajigaya are from the same field of endeavor, the teachings described by Nagata would have been recognized in the pertinent art of Kajigaya.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Nagata with the teachings of Kajigaya for the purpose of replacing normal memory cells that are defective, see Nagata’s page 1, par. 0002.
Regarding claim 17, Kajigaya in combination with Nagata teaches the limitations with respect to claim 15.
Furthermore, Nagata teaches wherein forming the 2D array of BLS transistors or the 2D array of BLP transistors comprises connecting one terminal of the transistor of each dummy memory cell to the global bit line or charging line (Fig. 3: one terminal of the transistor of RC is connected to GBL through LBL and SW).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 16, there is no teaching or suggestion in the prior art of record to provide the recited step of forming the 2D array of BLS transistors or the 2D array of BLP transistors comprises removing or shorting the capacitor of each dummy memory cell in the one of the planes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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