DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 9 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1 is ineligible.
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Step
Analysis
1. Statutory Category?
YES. This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites a series of steps and, therefore, is a process.
2A – Prong 1: Judicial Exception Recited?
YES. The claim recites the limitation of “f) determining a third numerical value (∆
T
^
) representative of a time offset between an instant when said first analog signal crosses a threshold and an instant when said second analog signal crosses said threshold or another threshold; and g) determining an estimate (
φ
^
'
) of said phase of the complex impedance of the electrical element as a function of said first, second and third numerical values and of a fourth numerical value representative of the frequency f of the excitation signal; wherein step g) comprises: g1) determining a first approximation
(
φ
^
'
) of said phase (
φ
) based on said third numerical value (∆
T
^
) representative of a time offset and on said fourth numerical value representative of the frequency f of the excitation signal; g2) determining a phase correction term (-Δ
φ
LH) as a function of the first and the second numerical value; g3) determining said estimate (
φ
^
'
) of the phase of the complex impedance of the electrical element by calculating the sum of said first approximation and said phase correction term”. The limitations of determining falls within the enumerated grouping of mathematical concept of calculation, which can be illustrated from the relevant portion of para [0038], para [0039], and para [0042]. This limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “measuring the phase”, nothing in the claim element precludes the limitation from practically being performed in the mind. For example, but for the “measuring the phase…” language, the claim encompasses a user manually determining. The formula does not have to be in the claim to have the limitation directed to an abstract concept. The mere nominal recitation of a generic computer element does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
2A – Prong 2: Integrated into a Practical Application?
NO. The claim recites an additional element: an electrical element… a device used for obtaining the data is recited at a high level of generality (i.e., as a general means of gathering the data for use in the determination), and amounts to mere data gathering, which is a form of insignificant extra-solution activity. The general steps of determining used to perform the method is also recited at a high level of generality, and merely automates the determination. Each of the additional limitations is no more than mere instructions to apply the exception using a generic computer component (the processor/program).
2B: Claim provides an Inventive Concept?
NO. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amounts to no more than mere instructions to apply the exception using a generic computer component.
The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
Dependent Claims(s) 2 – 5, when analyzed as a whole are held to be ineligible subject matter and are rejected under 35 U.S.C. § 101 because the additional recited limitations(s) fail(s) to establish that the claim is not directed to an abstract idea because the additional limitations(s) are no more than a field of use or merely involve insignificant extra-solution activity as data gathering and calculation.
Particularly:
Regarding Claims 2, 3, 4, and 5, are considered abstract ideas.
The claims have been considered ineligible under 35 USC 101 by reviewing both the limitations themselves and as ordered combinations of elements which do not amount to a practical application of the abstract limitations.
Allowable Subject Matter
Claims 6 – 9 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 6, the prior art of record does not teach claimed limitation: “a digital circuit (CN) configured to determine an estimate (
φ
^
'
) of said phase of the complex impedance of the electrical element as a function of a first numerical value (A) representative of an amplitude of said first digital signal (Uv), of a second numerical value (B) representative of an amplitude of said second digital signal (U1), of a third numerical value (∆
T
^
) representative of a time offset between the first square-wave signal (
U
-
v) and the second square-wave signal (
U
-
v) and of a fourth numerical value representative of the frequency f of the excitation signal” in combination with all other claimed limitations of claim 6.
Regarding Claims 7 – 9, the claims are allowed as they further limit allowed claim 6.
Comments
The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claim 1. Therefore, no prior art rejection for claim 1 is presented in this action. However, Claims 1 – 5 are rejected under 35 U.S.C. 101.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Cabanillas et al. (US 2025/0189567 A1) suggest an method for measuring the phase of the complex impedance of an electrical element (EL), comprising the following steps: a) applying an excitation signal (Sex) oscillating at a known frequency f to said electrical element; b) acquiring a first time-variable analog signal representative of a voltage across the terminals of the electrical element; c) acquiring a second time-variable analog signal representative of a current through the electrical element; d) determining a first numerical value representative of an amplitude of said first analog signal and a second numerical value representative of an amplitude of said second analog signal; e) carrying out thresholding with hysteresis of said first and said second analog signal; f) determining a third numerical value representative of a time offset between an instant when said first analog signal crosses a threshold and an instant when said second analog signal crosses said threshold or another threshold; and g) determining an estimate of said phase of the complex impedance of the electrical element as a function of said first, second and third numerical values and of a fourth numerical value representative of the frequency f of the excitation signal; wherein step g) comprises: g1) determining a first approximation of said phase based on said third numerical value representative of a time offset and on said fourth numerical value representative of the frequency f of the excitation signal; g2) determining a phase correction term as a function of the first and the second numerical value; g3) determining said estimate (custom-character) of the phase of the complex impedance of the electrical element by calculating the sum of said first approximation and said phase correction term (see claim 1).
Maki-Ontto et al. (US 11,828,779 B2) teaches a apparatus for measuring an impedance of an electrical load, wherein the electrical load is configured to be coupled with a current source that supplies an input current to the electrical load between a first terminal and a second terminal of the electrical load, the apparatus comprising: a transformer having a primary winding and a secondary winding, the secondary winding is configured to be coupled to the current source in parallel with the electrical load; a capacitance coupled in series with the secondary winding and configured to be coupled in parallel with the electrical load when the secondary winding is coupled to the current source; and a processing unit, wherein the processing unit is configured to: control an excitation signal that is applied to the primary winding so as to cause a variation, corresponding to the excitation signal, in the input current of the electrical load; measure the input current and an input voltage of the electrical load; and based on the measured input current and the measured input voltage, determine the impedance of the electrical load (see claim 1).
Zhou et al. (US 12,038,463 B2) disclose a system for determining impedances of a plurality of devices under test (DUT), the system comprising: a plurality of measurement circuits coupled to the plurality of DUTs, wherein the plurality of DUTs comprise electrical circuits, wherein each measurement circuit is configured to generate first voltage related data of a respective DUT; a fast Fourier transform (FFT) processor coupled to the plurality of measurement circuits, wherein the FFT processor is configured to convert each first voltage related data into a respective second voltage related data using a fast Fourier transform; and a controller coupled to the plurality of measurement circuits and the FFT processor, wherein the controller is configured to calculate an impedance of each DUT using the respective second voltage related data and output each impedance calculated thereby for characterization of performance of the electrical circuits within the plurality of DUTs (see claim 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 8/7/2026
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