Prosecution Insights
Last updated: July 17, 2026
Application No. 18/972,688

AUTOMATIC SINGLE-USE-DEVICE VOLTAGE COMPATIBILITY

Non-Final OA §102§103§112
Filed
Dec 06, 2024
Priority
Dec 15, 2023 — provisional 63/610,801
Examiner
PHAM, LY D
Art Unit
Tech Center
Assignee
Boston Scientific Scimed Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
970 granted / 1032 resolved
+34.0% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
24 currently pending
Career history
1046
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
34.1%
-5.9% vs TC avg
§102
36.5%
-3.5% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1032 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 4 is objected to because of the following informalities” In claim 4, line 2, “identity” is suggested to be amended to “identify”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 6 – 15 are system claims but also include limitations drawn to method step limitations. For example, claim 6 includes: “detecting…”; “selecting …”; and “translating…”. According to the section MPEP 2173.05(p), II. Product and Process in the same claim. “A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 USC 112(b) or pre-AIA 35 USC 112 second paragraph”. The Office therefore suggests that claim 6 be amended to read, as exemplarily follow: The system of claim 1, wherein operations are performed by the one or more processors configured to: detect the presence …; select a first voltage …; translating a single-use-device…. Similar amendments are suggested also for claims 7 – 15. Appropriate corrections/revisions are required in order to overcome this type of rejection. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3, 6 – 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cho et al. (US Pat Pub 2018/0101492). Regarding claim 1, Cho et al. disclose a system for adapting long-lived capital equipment to changing single-use-device data storage technology (for example figs. 1 – 6 and all related texts), the system comprising: one or more memory devices (for example the memory core 370, para 0047) storing instructions (considered to be intended use); one or more processors (referred to in abstract as host device, 110 of fig. 1 or 310 of fig. 3) configured to execute the instructions to perform operations (referred to in abstract as “send a query command”); a power supply configured to convert AC power into a plurality of DC voltages (referred to as the power management integrated circuit PMIC, fig. 1 or 3); a selector configured to select one of the plurality of DC voltages (referred to in abstract as “selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device”. In para 0042 as “host controller sends a power selection signal to the PMIC so that the PMIC produces either the 3.3V power supply voltage or the 2.5V power supply voltage based on the power selection signal…”); and a level shifter configured to receive the selected one of the plurality of DC voltages (for example the plurality of DC voltages of 2.5V, 1.2V, 1.8V, and 1.2V from PMIC unit) and to translate a single-use-device data storage voltage (one of 190, 180 or 170, fig. 1, for example) to the selected one of the plurality of DC voltages (referred to in fig. 1 or 3 as any single voltage of either VCC = 3.3V or 2.5V, VCCQ = 1.2V, VCCQ2 = 1.8V, or REFCLK = 1.2V, for use for the respective device of either the UFS device controller, the I/O device 180/380, or the memory core device 170/370). Regarding claim 3, Cho et al. also disclose the system of claim 1, wherein the selector is a digital switch voltage rail selector or a digitally controlled voltage raid that is controlled by a configuration file (referred to in fig. 1 as the ROM 145 and fuse array 140 as digital switch or configuration file. Also, device information 395 of fig. 3 comprises configuration information to control voltage selection by host controller 320, as described in para 0058 and 0061 – 0064). Regarding claim 16, Cho et al. disclose a method for adapting long-lived capital equipment to changing single-use-device data storage technology, the method comprising: detecting the presence of a single-use-device data storage; selecting a first voltage of the plurality of DC voltages, the first voltage being a lowest of the plurality of DC voltages (as described in para 0058, proper voltage supply for the memory device 360 is performed when first powered up after installation in storage device 350. See also S410 and S470 of fig. 5 and para 0061-00632. See also para 0066 and fig. 6); selecting a first voltage of a plurality of DC voltages from a power supply (this is implemented by host controller 320 of fig. 3, as described in para 0042. In step S420 of fig. 5, a first voltage is selected. This voltage can be 2.5V or even 1.8 V as shown in fig. 6, see also para 0061, 0062, and 0066, etc.…); translating a single-use-device data storage voltage to the first voltage of the plurality of DC voltages (implemented by PMIC 330 itself, as described in para 0046, 0047, and 0059 – 0066. See also fig. 6); and performing a first test message exchange with the detected single use storage device (host controller 320 sends query command in S440 of fig. 5; in S450 of fig. 5, device controller 390 replies or not to his command, as described in para 0063 and 0064). Claims 6 and 7 are also rejected based on grounds for the rejection of claims 1 and 16 above. Regarding claims 8 – 15 and 17 – 20, Cho et al. also disclose the system/method as set forth above, wherein the operations include: locking in the first voltage of the plurality of DC voltages at the selector if the first test message exchange is successful, wherein the operations include: selecting a second voltage of the plurality of DC voltages, the second voltage being a higher voltage than the first voltage of the plurality of DC voltages, if the first test message exchange is unsuccessful; and translating the single-use-device data storage voltage to the second voltage of the plurality of DC voltages (step-by-step increase of the power supply voltage supplied to the memory device 360 (see para 0066), comprising three or more power supply voltages as in fig. 6, each step associated with message exchanging and voltage locking when the device controller 390 responds, as in S440 and S450 of fig. 56 and also in para 0064 and 0065), selecting a fourth voltage of the plurality of DC voltages, the fourth voltage being a higher voltage than the third voltage of the plurality of DC voltages, if the third test message exchange is unsuccessful; and translating the single-use-device data storage voltage to the fourth voltage of the plurality of DC voltages (see further para 0066, referred to as “three or more levels of power supply voltages”). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US Pat Pub 2018/0101492) in view of Singh et al. (US Pat 9,299,419). Regarding claim 2, Cho et al. also disclose the system of claim 1, except wherein the selector is a manual voltage rail selector. This feature is however taught by Singh et al. (see col. 6, lines 34 – 39). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the references as cited, so that the accurate adjustment of Vdd supply to the memory is enabled. Allowable Subject Matter Claims 4 – 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record fail to teach or reasonably suggest the system/method as set forth above, further comprising, in combination, the features and limitation additionally claimed at least in claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LY D PHAM/Primary Examiner, Art Unit 2827 June 18, 2026
Read full office action

Prosecution Timeline

Dec 06, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.3%)
1y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1032 resolved cases by this examiner. Grant probability derived from career allowance rate.

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