DETAILED ACTION
The action is responsive to the following communications: the Application filed December 09, 2024 and the information disclosure statement (IDS) filed December 09, 2024 and June 03, 2025. This application is a CON of 18/344,459.
Claims 1-20 are pending. Claims 1, 10 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 09, 2024 and June 03, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,198,754. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,198,754
Comment
Claim 10. A device, comprising:
a memory array comprising a plurality of tracking cells;
a tracking bit line coupled to the plurality of tracking cells at a first node;
a timing control circuit coupled to the tracking bit line and comprising: a sense circuit comprising a first number of first transistors and a second number, different from the first number, of second transistors, wherein the first transistors and the second transistors are coupled in series between first and second voltage terminals and configured to generate a negative bit line enable signal in response to that a voltage level on the first node being below a threshold voltage value of the sense circuit; and
a write assist circuit configured to provide a voltage below a ground level to the memory array according to the negative bit line enable signal.
Claim 1. A device, comprising:
a timing control circuit comprising:
a sense circuit coupled to a plurality of tracking cells through a tracking bit line at a first node, and comprising a first number of first transistors and a second number, different from the first number, of second transistors that are coupled in series between first and second terminals and have gate terminals coupled to the first node,
wherein the sense circuit is configured to generate, at a second node coupled between the first and second transistors, a negative bit line enable signal in response to that a voltage level on the first node is below a threshold voltage value of the sense circuit; and
a write assist circuit configured to pull down a voltage level on a bit line or a complement bit line of a memory array in response to a negative bit line trigger signal converted from the negative bit line enable signal.
Note footnote1
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a first number of first transistors and a second number, different from the first number, of second transistors that have gate terminals coupled together to a plurality of tracking cells”. There is not disclosure the claimed limitation(s) from the specification. So these languages constitute new matter.
Claims 2-9 are rejected due to claim dependency.
Regarding claims 1-9 the art rejection, the claimed terms may be indefinite (see 112 rejections above) and there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, so it would not be proper to reject such a claim on the basis of prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 and 14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chander et al. (US 9,812,191) in view of Wang (US 2010/0284232).
Regarding independent claim 10, Chander et al. teach a device, comprising:
a sense circuit comprising a first number of first transistors (see FIG. 4: 112) and a second number, different from the first number, of second transistors (FIG. 4: 116-144), wherein the first transistors and the second transistors are coupled in series between first and second voltage terminals (see FIG. 4 along with FIG. 2) and configured to generate a negative bit line enable signal (FIG. 2: 151) in response to that a voltage level on the first node being below a threshold voltage value of the sense circuit (see col. 11, lines 22-47: … monitor a voltage level on the node X (as described above with respect to FIG. 2), and once the voltage level at the node X drops below the trip point (e.g., 30% Vdd) … outputs the negative bit line control signal 605 at HIGH.); and
a write assist circuit configured to provide a voltage below a ground level to the memory array according to the negative bit line enable signal (see e.g., col. 11, lines 16-21: … to generate a negative voltage for a BL …) (see e.g., FIG. 2 and accompanying disclosure).
Chander et al’ bit cells and bit line do not explicitly disclose tracking bit cells and bit line.
However, Chander’s invention relates to the memory cells with negative bit line voltage assist circuitry. The tracking cells and memory bit cells used in the negative bit line assist circuitry are well-known technology for a type memory for its purpose.
For support, of the above asserted facts, see for example, Wang, i.e., a memory array comprising a plurality of tracking cells (FIG. 6: 604 and FIG. 10: 1002-1008);
a tracking bit line (FIG. 10: DMY_BL) coupled to the plurality of tracking cells at a first node (DMY_BL);
a timing control circuit coupled to the tracking bit line (see FIG. 6 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Wang to the teaching of Chander et al. such that a memory, as taught by Chander et al., utilizes tracking circuitry, as taught by Wang, for the purpose of enhancing write operation used during write assist operations.
Regarding claim 11, Chander et al. and Wang, as combined, teach the limitations of claim 10
Chander et al. further teach the timing control circuit further comprises: an inverter configured to convert the negative bit line enable signal into a negative bit line trigger signal, wherein the write assist circuit is triggered by the negative bit line trigger signal to pull down the voltage level on a bit line or a voltage level on a complement bit line to a transient negative voltage level (e.g., FIG. 2 and accompanying disclosure).
Regarding claim 12, Chander et al. and Wang, as combined, teach the limitations of claim 10
Wang further teaches the sense circuit comprises: a Schmitt trigger (FIG. 10: 1010, and para. 0042: … the signal generating unit 1010 is a Schmitt trigger …) configured to generate the negative bit line enable signal in response to that the voltage level on the first node downward passes a low threshold voltage value of the Schmitt trigger (FIGS. 6 and 10, and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Wang et al. for the same purpose of enhancing write operation used during write assist operations.
Regarding claim 14, Chander et al. and Wang, as combined, teach the limitations of claim 10
Wang’s memory cell array (FIG. 6) does not explicitly an amount of the tracking cells coupled with the tracking bit line is substantially equal to an amount of cell rows in the memory array.
However, the claimed equal amount of cell rows are well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize balanced tracking cells because these conventional technology are well established in the art of the memory devices.
Claim 17 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 2010/0284232) in view of Chander et al. (US 9,812,191).
Regarding independent claim 17, Wang teaches a device, comprising:
a plurality of tracking cells (FIG. 6: 604 and FIG. 10: 1002-1008) coupled to a tracking bit line (DMY_BL);
a sense circuit (FIG. 6: 616 including FIG. 10: 1010) coupled to the tracking bit line (FIG. 10: DMYBL (see FIGS. 6 and 10: SAE)), and comprising a Schmitt trigger (FIG. 10: 1010, and para. 0042: … the signal generating unit 1010 is a Schmitt trigger …).
Wang does not explicitly disclose wherein the sense circuit is configured to pull down a negative bit line trigger signal in response to a voltage level on the tracking bit line downward crossing a threshold voltage value of the Schmitt trigger; and a write assist circuit comprising a capacitor coupled between the negative bit line trigger signal and a bit line voltage, wherein the capacitor is configured to pull down the bit line voltage in response to the negative bit line trigger signal pulled down.
Chander et al. teach the deficiencies, i.e., wherein the sense circuit is configured to pull down a negative bit line trigger signal in response to a voltage level on the tracking bit line downward crossing a threshold voltage value of the Schmitt trigger (see col. 11, lines 22-47: … Accordingly, the Schmitt trigger 604 may be able to monitor a voltage level on the node X (as described above with respect to FIG. 2), and once the voltage level at the node X drops below the trip point (e.g., 30% Vdd) of the Schmitt trigger 604, the Schmitt trigger 604 outputs the negative bit line control signal 605 at HIGH.); and
a write assist circuit comprising a capacitor (e.g., FIG. 2: 154) coupled between the negative bit line trigger signal (e.g., FIG. 2: 151) and a bit line voltage (see e.g., col. 11, lines 16-21: … boosting capacitor … to generate a negative voltage for a BL …), wherein the capacitor is configured to pull down the bit line voltage in response to the negative bit line trigger signal pulled down (see e.g., FIG. 2 and accompanying disclosure).
Chander et al’ bit line do not explicitly disclose tracking bit line.
However, Chander’s invention relates to the memory cells with negative bit line voltage assist circuitry. The tracking cells and memory bit cells used in the negative bit line assist circuitry are well-known technology for a type memory for its purpose.
For support, of the above asserted facts, see for example, Chen (US 2013/01484838), FIG. 2 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chander et al. to the teaching of Wang such that a memory, as taught by Wang, utilizes negative bit line and write circuitry, as taught by Chander et al., for the purpose of utilizing negative bit line circuitry in replica memory (e.g. SRAM) system, thereby enhancing write operation used during write assist operations.
Allowable Subject Matter
Claims 13, 15-16 and 18-20 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 10 and 17, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights