Prosecution Insights
Last updated: October 01, 2026
Application No. 18/973,509

ELECTRONIC DEVICE AND IMPEDANCE MEASUREMENT METHOD

Non-Final OA §102
Filed
Dec 09, 2024
Priority
Jan 04, 2024 — CN 202410014193.X
Examiner
SHAH, NEEL D
Art Unit
Tech Center
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
549 granted / 632 resolved
+26.9% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
20 currently pending
Career history
647
Total Applications
across all art units

Statute-Specific Performance

§101
9.6%
-30.4% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
21.6%
-18.4% vs TC avg
§112
14.8%
-25.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 632 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority 2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202410014193.X, filed on 1/4/24. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 12/9/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claims 1-2, 4-9 and 16 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Fries et al. (US 5,270,673). (“Fries”). 6. Regarding claim 1, Fries teaches An electronic device [Figures 1-6, an electronic device is shown], comprising: a housing [Figures 1-6, housing 20/24]; a panel, disposed on the housing [Figures 1-6, a panel 26, disposed on the housing is shown]; and a circuit board, electrically connected to the panel, wherein the circuit board has a first ground terminal and a second ground terminal, and the first ground terminal and the second ground terminal have no electrical connection path within the circuit board [Figures 1-6, a circuit board 34, electrically connected to the panel is shown, ground terminals 30/47 shown], and the first ground terminal is electrically connected to the housing through a first conductive medium, and the second ground terminal is electrically connected to the housing through a second conductive medium [Figures 1-6, the connection is shown]. 7. Regarding claim 2, Fries teaches further comprising: a flexible circuit board electrically connected to the panel through the flexible circuit board [Figures 1-6, a flexible circuit board 92 is shown]. 8. Regarding claim 4, Fries teaches wherein the circuit board has a first side and a second side opposite to each other in a top view, and the first ground terminal is close to the first side, and the second ground terminal is close to the second side [Figures 1-6, the circuit board 34 has a first side and a second side as shown]. 9. Regarding claim 5, Fries teaches wherein the first ground terminal and the second ground terminal are located on the same surface of the circuit board [Figures 1-6, see the first and the second ground terminals 30/47]. 10. Regarding claim 6, Fries teaches wherein the first ground terminal and the second ground terminal are located on opposite surfaces of the circuit board [Figures 1-6, see the first and the second ground terminals 30/47]. 11. Regarding claim 7, Fries teaches wherein the second ground terminal surrounds the first ground terminal in a top view [Figures 1-6, see the first and the second ground terminals 30/47]. 12. Regarding claim 8, Fries teaches wherein an ratio of the area of the first ground terminal and the area of the second ground terminal is between 0.04 and 1 [Figures 1-6, see the first and the second ground terminals 30/47]. 13. Regarding claim 9, Fries teaches wherein the first ground terminal has a first characteristic length, the second ground terminal has a second characteristic length, and the first characteristic length is between 3 mm and the second characteristic length [Figures 1-6, see the first and the second ground terminals 30/47]. 14. Regarding claim 16, Fries teaches wherein the first conductive medium and the second conductive medium are separated from each other [Figures 1-6, the conductive medium are separated from each other]. Claim Objections 15. Claims 3, 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 3. The electronic device as claimed in claim 1, further comprising: a connector disposed on the circuit board and comprising a first contact and a second contact, wherein the first contact is electrically connected to the first ground terminal, and the second contact is electrically connected to the second ground terminal. 10. The electronic device as claimed in claim 1, wherein the circuit board comprises a first line and a second line electrically connected to the first ground terminal and the second ground terminal, respectively. 11. The electronic device as claimed in claim 10, wherein the first line and the second line extends horizontally at different heights in the circuit board. 12. The electronic device as claimed in claim 11, wherein the first line and the second line overlap in a normal direction of the circuit board. 13. The electronic device as claimed in claim 1, wherein the housing comprises a first conductive part and a second conductive part connected to each other, and the first conductive part and the second conductive part are electrically connected to the first conductive medium and the second conductive medium, respectively. 14. The electronic device as claimed in claim 1, wherein the first ground terminal is exposed in a first ground opening in an insulating layer of the circuit board. 15. The electronic device as claimed in claim 14, wherein a contact area of the first conductive medium and the first ground terminal is larger than half of an area of the first ground opening in a top view. Allowable Subject Matter 16. Claims 17-20 are allowed. 17. The following is an examiner’s statement of reasons for allowance: 18. Regarding claim 17, Fries teaches An impedance measurement method, comprising: disposing a housing; disposing a circuit board, wherein the circuit board has a first ground terminal and a second ground terminal, and the first ground terminal and the second ground terminal have no electrical connection path within the circuit board, and the first ground terminal is electrically connected to the housing through a first conductive medium, and the second ground terminal is electrically connected to the housing through a second conductive medium [Figures 1-6, housing 20/24, circuit board 34, ground terminals 30/47, terminal connection is shown]. The prior art of record taken alone or in combination fails to teach or suggest the limitation of “disposing a test board to provide a constant current to the first ground terminal and output a voltage value; and measuring an impedance value through the voltage value” in combination with other limitations of the claim. 19. Claims 18-20 are also allowed as they further limit claim 17. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Grellman, H. Erwin (US 4600907), Figures 1-2 shows a circuit board, chip/die, terminal points, housing and so on arranged in a similar fashion to that of the present application. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEEL D SHAH whose telephone number is (571)270-3766. The examiner can normally be reached M-F: 9AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NEEL D SHAH/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Dec 09, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.6%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 632 resolved cases by this examiner. Grant probability derived from career allowance rate.

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