DETAILED ACTION
The action is responsive to the following communications: the Application filed December 09, 2024 and the information disclosure statement (IDS) filed December 09, 2024 and June 03, 2025. This application is a CON of 18/344,459.
Claims 1-20 are pending. Claims 1, 10 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 09, 2024 and June 03, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,198,754. Although the claims at issue are not identical, they are not patentably distinct from each other.
Although Instant Application is a DIV of Application No. 18/344,459, the amendment of the Parent Application contains the subject matter of the instant application. Therefore, the examiner treats the instant application as a continuation application. See the following for more details.
A nonstatutory double patenting rejection may be appropriate in situations in which the invention presented in the divisional is not the same invention that was the subject of the restriction requirement (see MPEP 804.04).
Instant Application
US Patent 12,198,754
Comment
Claim 7. A circuit, comprising:
a memory array comprising a plurality of tracking cells;
a tracking bit line coupled between a first node and the plurality of tracking cells;
a timing control circuit coupled to the first node and comprising: a Schmitt trigger configured to generate a negative bit line enable signal in response to that a voltage level on the first node, wherein the timing control circuit is configured to generate a negative bit line trigger signal according to the negative bit line enable signal; and
a write assist circuit comprising a transistor configured to be turned off in response to the negative bit line trigger signal to adjust a voltage level on a bit line.
Claim 17. A device, comprising:
a plurality of tracking cells coupled to a tracking bit line;
a sense circuit coupled to the tracking bit line, and comprising a Schmitt trigger, wherein the sense circuit is configured to increase a voltage level of a negative bit line enable signal in response to a voltage level on the tracking bit line downward crossing a threshold voltage value of the Schmitt trigger; and
a write assist circuit configured to pull down a voltage level on a bit line for a write operation of a memory array according to a negative bit line trigger signal converted from the negative bit line enable signal.
Note footnote1
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-9, 11, 14-16 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chander et al. (US 9,812,191) in view of Chen (US 2013/0148438).
Regarding independent claims 1, 7 and 14, Chander et al. teach a circuit, comprising:
a memory array (e.g., FIG. 2 and 5: 102A) comprising a plurality of tracking cells (102);
a tracking bit line coupled between a first node (FIG. 2: X) and the plurality of tracking cells (102); and
a timing control circuit coupled to the first node and comprising:
a Schmitt trigger (FIG. 6A: 634 (seems typo, which should be 604)) configured to generate a negative bit line enable signal in response to a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger (see col. 11, lines 22-47: … Accordingly, the Schmitt trigger 604 may be able to monitor a voltage level on the node X (as described above with respect to FIG. 2), and once the voltage level at the node X drops below the trip point (e.g., 30% Vdd) of the Schmitt trigger 604, the Schmitt trigger 604 outputs the negative bit line control signal 605 at HIGH.),
wherein the timing control circuit is configured to generate a negative bit line trigger signal (FIG. 6A: Z, and e.g., col. 11, lines 16-21: … boosting capacitor … to generate a negative voltage for a BL …) according to the negative bit line enable signal (605) for adjusting voltage levels of a plurality of bit lines of the memory array (see BL voltage).
Chander et al’ bit cells and bit line do not explicitly disclose tracking cells and tracking bit line.
However, Chander’s invention relates to the memory cells with negative bit line voltage assist circuitry. The tracking cells and memory bit cells used in the negative bit line assist circuitry are well-known technology for a type memory for its purpose.
For support, of the above asserted facts, see for example, Chen, FIG. 2 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chen et al. to the teaching of Chander et al. such that a memory, as taught by Chander et al., utilizes negative bit line enable circuitry with tracking bit cells, as taught by Chen, for the purpose of utilizing negative bit line circuitry in replica memory (e.g. SRAM) system, thereby enhancing write operation used during write assist operations.
Regarding claims 2, 8 and 15, Chander et al. and Chen, as combined, teach the limitations of claims 1, 7 and 14, respectively.
Chander et al. and Chen further teach the timing control circuit further comprises: an inverter configured to convert the negative bit line enable signal into the negative bit line trigger signal, wherein the negative bit line trigger signal is transmitted to a write assist circuit, and the write assist circuit is triggered by the negative bit line trigger signal to pull down a bit line voltage or a complement bit line voltage to a transient negative voltage level (see Chander’s FIGS. 2, 5 and 6; Chen’s FIG. 2, and accompanying disclosure).
Regarding claims 4, 11 and 18, Chander et al. and Chen, as combined, teach the limitations of claims 1, 7 and 14, respectively.
Chen further teaches an amount of the tracking cells coupled with the tracking bit line is substantially equal to an amount of cell rows in the memory array (FIG. 1; further it’s a well-known technology).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Chen for the same purpose of enhancing write operation used during write assist operations, further these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 16, Chander et al. and Chen, as combined, teach the limitations of claims 7 and 14, respectively.
Chander et al. further teach the Schmitt trigger generates the negative bit line enable signal in response to that the voltage level on the first node downward passes a low threshold voltage value of the Schmitt trigger (see FIG. 6A and accompanying disclosure, e.g., col. 11, lines 22-47).
Allowable Subject Matter
Claims 3, 5-6, 10, 12-13, 17 and 19-20 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 7 and 14, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights