Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated July 31, 2026, claims 1-16 are active in
this application.
Election
Arles A. Taylor Jr. [Reg. No. 39,395] made a provisional election without traverse to prosecute
the invention of Group 1 directed to Digital stores using particular elements for associative storage, claims 1-16. Affirmation of this election was made in the response to the restriction requirements.
Claim 17 is withdrawn from further consideration by the Examiner, 37
C.F.R. § 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancellation of claims to a non-
elected invention, the inventorship must be amended in compliance with 37 C.F.R. § 1.48(b) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. Any amendment of inventorship must be accompanied by a diligently-filed petition under 37 C.F.R. § 1.48(b) and by the fee required under 37 C.F.R. § 1.17(h).
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed July 31, 2026 have been considered.
Claim Objections
Claims 3-5, 8, 11-14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitagawa et al. [US Patent Application # 20120020141].
With respect to claim 1, Kitagawa et al. discloses a method for controlling an analog memory cell using a non-volatile memory (NVM) element, the method comprising: applying an analog voltage to a gate of a select transistor [“…the electric potential of the word line WL rises by typically a voltage amplitude having the same magnitude as the power-supply voltage Vdd. The nodes at which an analog voltage having a magnitude other than the voltage amplitude of the same magnitude as the power-supply voltage Vdd is driven are only a transistor gate electrode to which the set gate voltage Vgset is applied and a transistor gate electrode to which the reset gate voltage Vgrst is applied….” – par. 0215]; providing, by the select transistor, a substantially constant current through the NVM element [“…the voltage applied to the gate electrode of the access transistor is adjusted in order to control the magnitude of a current flowing through the memory element as a current for making the resistance of the memory element small or large….” – pars. 0010 and 0017]; and causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) ["...after the state inversion from the high-resistance state HRS to the low-resistance state LRS..." and "...after the inversion to the set operation..." – par. 0250 (The core event in both phrases is identical. The application phrase describes the transition of the "NVM element," which directly maps to the reference phrase's "state inversion" of the variable-resistance element (Re) from HRS to LRS during a "set operation.")], causing a voltage drop across the NVM device ["Thus, a relatively small voltage expressed by the product of (Rcell.times.Iset) is applied between the two ends of the variable-resistance element Re..." – par. 0250 (A voltage "applied between the two ends" of a resistor is fundamentally the definition of a "voltage drop" across it. Both phrases describe how the electrical state changes result in a specific voltage across the memory element (V = I x R), with the reference phrase explicitly providing Ohm's law (R_cell x I_set)) to quantify this drop.)] and resulting resistance drop toward a target LRS resistance level ["The current flowing after the state inversion from the high-resistance state HRS to the low-resistance state LRS is the set current Iset... Thus, also after the inversion to the set operation, the sustainment of the reliability..." – par. 0250 (The application describes the end result of the process—the element dropping to a stable, target LRS resistance. The reference maps to this by explaining that once the inversion happens, the system settles into a stable "set current (I_set)" state at a specific cell resistance (R_cell)] directly proportional to the analog voltage applied to the gate of the select transistor ["During this state inversion operation, the operating point moves to a saturation area along the curve representing the saturation characteristic of the drain of the NMOS transistor, limiting the flowing current." – par. 0250 (The application focuses on how the final resistance level is controlled by the voltage applied to the gate of a select transistor. The reference explains the exact physical mechanism behind this control: an NMOS transistor (the "select transistor") enters its "saturation area," which inherently limits the current (I_set). In semiconductor physics, the saturation current of an NMOS transistor is directly determined by its gate voltage (V_gs). Therefore, limiting the current via transistor saturation (Reference) is the exact mechanism used to make the operation proportional to the gate voltage (Application).)].
With respect to claim 2, Kitagawa et al. discloses the voltage drop across the NVM device is large enough to cause the NVM element to switch and cause the resistance drop based on the analog voltage applied to the gate of the select transistor. See par. 0250. In the cited section, Kitagawa et al. emphasizes that the voltage after the transition is "relatively small" to avoid "voltage stress" and ensure "reliability," it inherently teaches that a switching voltage must be applied to trigger the operation. The reference mentions "During this state inversion operation..." and "after the inversion to the set operation...". For a state inversion to occur in a variable-resistance element, the initial voltage drop across it must inherently exceed its threshold switching voltage.
With respect to claim 6, Kitagawa et al. discloses the NVM element comprises at least one of: a metal-oxide memristor, a phase change memory (PCM) device, and a magnetic tunnel junction (MTJ) element. See figs. 1-5.
With respect to claim 7, Kitagawa et al. discloses causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) comprises limiting a range for analog resistance values to be within a continuous device specific resistance range. See par. 0250. In the cited section, Kitagawa et al. states that during the "state inversion operation" (switching), the NMOS transistor enters its "saturation area" to limit the current to (I_set). For a transistor to control and limit the current precisely during a state change, the voltage applied across the overall cell must be high enough to initiate the switch (causing the inversion from HRS to LRS).
Claim(s) 9, 10 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitagawa et al. [US Patent Application # 20120020141].
With respect to claim 9, Kitagawa et al. discloses a current-controlled analog memory circuit comprising: a non-volatile memory (NVM) element [Re of fig. 2]; and a select transistor [AT] coupled to the NVM element and configured to store an analog value as a resistance of the NVM element by providing a substantially constant current through the NVM element [“…the voltage applied to the gate electrode of the access transistor is adjusted in order to control the magnitude of a current flowing through the memory element as a current for making the resistance of the memory element small or large….” – pars. 0010 and 0017] and causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) ["...after the state inversion from the high-resistance state HRS to the low-resistance state LRS..." and "...after the inversion to the set operation..." – par. 0250 (The core event in both phrases is identical. The application phrase describes the transition of the "NVM element," which directly maps to the reference phrase's "state inversion" of the variable-resistance element (Re) from HRS to LRS during a "set operation.")], causing a voltage drop across the NVM device ["Thus, a relatively small voltage expressed by the product of (Rcell.times.Iset) is applied between the two ends of the variable-resistance element Re..." – par. 0250 (A voltage "applied between the two ends" of a resistor is fundamentally the definition of a "voltage drop" across it. Both phrases describe how the electrical state changes result in a specific voltage across the memory element (V = I x R), with the reference phrase explicitly providing Ohm's law (R_cell x I_set)) to quantify this drop.)] and resulting resistance drop toward a target LRS resistance level directly proportional to an analog voltage applied to a gate of the select transistor ["The current flowing after the state inversion from the high-resistance state HRS to the low-resistance state LRS is the set current Iset... Thus, also after the inversion to the set operation, the sustainment of the reliability..." – par. 0250 (The application describes the end result of the process—the element dropping to a stable, target LRS resistance. The reference maps to this by explaining that once the inversion happens, the system settles into a stable "set current (I_set)" state at a specific cell resistance (R_cell)] directly proportional to the analog voltage applied to the gate of the select transistor ["During this state inversion operation, the operating point moves to a saturation area along the curve representing the saturation characteristic of the drain of the NMOS transistor, limiting the flowing current." – par. 0250 (The application focuses on how the final resistance level is controlled by the voltage applied to the gate of a select transistor. The reference explains the exact physical mechanism behind this control: an NMOS transistor (the "select transistor") enters its "saturation area," which inherently limits the current (I_set). In semiconductor physics, the saturation current of an NMOS transistor is directly determined by its gate voltage (V_gs). Therefore, limiting the current via transistor saturation (Reference) is the exact mechanism used to make the operation proportional to the gate voltage (Application).)].
With respect to claim 10, Kitagawa et al. discloses the voltage drop across the NVM device is large enough to cause the NVM element to switch and cause the resistance drop based on the analog voltage applied to the gate of the select transistor. See par. 0250. In the cited section, Kitagawa et al. emphasizes that the voltage after the transition is "relatively small" to avoid "voltage stress" and ensure "reliability," it inherently teaches that a switching voltage must be applied to trigger the operation. The reference mentions "During this state inversion operation..." and "after the inversion to the set operation...". For a state inversion to occur in a variable-resistance element, the initial voltage drop across it must inherently exceed its threshold switching voltage.
With respect to claim 15, Kitagawa et al. discloses causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) comprises limiting a range for analog resistance values to be within a continuous device specific resistance range. See par. 0250. In the cited section, Kitagawa et al. states that during the "state inversion operation" (switching), the NMOS transistor enters its "saturation area" to limit the current to (I_set). For a transistor to control and limit the current precisely during a state change, the voltage applied across the overall cell must be high enough to initiate the switch (causing the inversion from HRS to LRS).
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 3. (Original) The method of claim 1 comprising reading the analog memory cell by providing a substantially constant current through the NVM element.
-with respect to claim 8. (Original) The method of claim 1 wherein causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) comprises limiting a range for analog resistance values to range from about 3 kQ to about 15 kQ.
-with respect to claim 11. (Original) The current-controlled analog memory circuit of claim 9 wherein the select transistor is configured for reading the analog memory circuit by providing a substantially constant current through the NVM element.
-with respect to claim 16. (Original) The current-controlled analog memory circuit of claim 9 wherein causing the NVM element to transition from a high resistance state (HRS) to a low resistance state (LRS) comprises limiting a range for analog resistance values to range from about 3 kQ to about 15 kQ.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 9, 2026
Prosecution Insights