DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,205,653. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 are anticipated by claims 1-20 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory device comprising:
an array of memory cells associated with multiple wordlines (claim 1, lines 2-5); and
control logic operatively coupled with the array, wherein the control logic, in performing a read operation, is to perform operations comprising:
determining a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline (claim 1, lines 9-12);
selecting a delay time based on whether the length of time is associated with a transient state or a non-transient state; and
reading the data from the memory cell associated with the selected wordline after the selected delay time (claim 1, lines 13-21).
Regarding claim 2, claim 2 of the patent recites the memory device of claim 1, further comprising a counter, wherein tracking the length of time comprises:
starting the counter upon beginning to ramp a voltage of the selected wordline; and
stopping the counter in response to the selected wordline reaching a threshold percentage of the pass voltage.
Regarding claim 3, claim 3 of the patent recites the memory device of claim 2, wherein the operations further comprise reading a value of the counter to determine the length of time.
Regarding claim 4, claim 4 of the patent recites the memory device of claim 1, wherein the operations further comprise:
comparing the length of time with time period values in a lookup table to determine whether the length of time satisfies at least one of a first threshold criterion or a second threshold criterion that is longer than the first threshold criterion;
in response to the length of time satisfying the first threshold criterion, causing a first delay time to pass before reading the data from the memory cell; and
in response to the length of time satisfying the second threshold criterion, causing a second delay time to pass before reading the data from the memory cell, the second delay time being longer than the first delay time.
Regarding claim 5, claim 5 of the patent recites the memory device of claim 4, wherein the first threshold criterion corresponds to a pillar of the array starting at a negative voltage.
Regarding claim 6, claim 6 of the patent recites the memory device of claim 4, wherein the second threshold criterion corresponds to a pillar of the array starting at an approximately zero voltage.
Regarding claim 7, claim 7 of the patent recites the memory device of claim 4, wherein the operations further comprise, in response to the length of time satisfying a third threshold criterion that is longer than the second threshold criterion, causing a third delay time to pass before reading the data from the memory cell, the third delay time being longer than the second delay time.
Regarding claim 8, claim 8 of the patent recites the memory device of claim 4, wherein the second delay time comprises a delay that is caused in response to a first read access of the array after being programmed.
Regarding claim 9, claim 9 of the patent recites the memory device of claim 4, wherein the first delay time comprises a delay that is caused in response to read accesses of the array that are subsequent to a first read access of the array after being programmed.
Regarding claim 10, claim 10 of the patent recites a system comprising:
a memory device comprising an array of memory cells associated with multiple wordlines; and
a processing device operatively coupled with the memory device, the processing device to perform operations comprising:
selecting a delay time, of multiple delay times, based on whether a read operation performed on a memory cell of the array is a first read access of the array since being programmed; and
causing control logic of the memory device to wait the selected delay time after a selected wordline of the memory cell has reached a pass voltage before reading data from the memory cell.
Regarding claim 11, claim 11 of the patent recites the system of claim 10, wherein the delay time is a first delay time, and wherein the operations further comprise:
determining that a second read operation performed on the array is a second read access of the array; and
communicating to the control logic to use a second delay time, of the multiple delay times, after the selected wordline of a selected memory cell has reached the pass voltage and before reading data from the selected memory cell, wherein the second delay time is shorter than the first delay time.
Regarding claim 12, claim 12 of the patent recites the system of claim 11, wherein the memory cells of the array are associated with a pillar of the array, the second delay time is associated with a transient state of the pillar, and wherein the operations further comprise:
detecting the pillar exit from the transient state; and
sending, together with a subsequent read operation, a command to the control logic to again use the first delay time.
Regarding claim 13, claim 13 of the patent recites the system of claim 12, wherein the detecting the pillar exit from the transient state comprises one of:
detecting a reset of the voltage of the pillar;
detecting the memory device satisfy a threshold temperature; or
detecting a period of time pass that is associated with the pillar returning to an approximately zero voltage.
Regarding claim 14, claim 14 of the patent recites a method comprising:
determining, by control logic of a memory device that includes an array of memory cells with which are associated with multiple wordlines, a length of time that a selected wordline, of multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline to perform a read operation;
selecting, by the control logic, a delay time based on whether the length of time is associated with a transient state or a non-transient state; and
reading the data from the memory cell associated with the selected wordline after the selected delay time.
Regarding claim 15, claim 15 of the patent recites the method of claim 14, further comprising:
starting a counter upon beginning to ramp a voltage of the selected wordline;
stopping the counter in response to the selected wordline reaching a threshold percentage of the pass voltage; and
reading a value of the counter to determine the length of time.
Regarding claim 16, claim 16 of the patent recites the method of claim 14, further comprising
comparing the length of time with time period values in a lookup table to determine whether the length of time satisfies at least one of a first threshold criterion or a second threshold criterion that is longer than the first threshold criterion;
in response to the length of time satisfying the first threshold criterion, causing a first delay time to pass before reading the data from the memory cell; and
in response to the length of time satisfying the second threshold criterion, causing a second delay time to pass before reading the data from the memory cell, the second delay time being longer than the first delay time.
Regarding claim 17, claim 17 of the patent recites the method of claim 16, wherein the first threshold criterion corresponds to a pillar of the array starting at a negative voltage, and wherein the second threshold criterion corresponds to the pillar starting at an approximately zero voltage.
Regarding claim 18, claim 18 of the patent recites the method of claim 16, further comprising, in response to the length of time satisfying a third threshold criterion that is longer than the second threshold criterion, causing a third delay time to pass before reading the data from the memory cell, the third delay time being longer than the second delay time.
Regarding claim 19, claim 19 of the patent recites the method of claim 16, wherein the second delay time comprises a delay that is caused in response to a first read access of the array after being programmed.
Regarding claim 20, claim 20 of the patent recites the method of claim 16, wherein the first delay time comprises a delay that is caused in response to read accesses of the array that are subsequent to a first read access of the array after being programmed.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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