DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claims because the examined application claim is either anticipated by, or would have been obvious over, the reference claims.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent #12,189,570. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claims 1-8 in the claimed invention claims the same compiler with addition of its compilation target (array of reconfigurable units and a configuration module).
Claims 9-16 in the claimed invention claims the same compiler with replacing “n computational nodes” with “a plurality of pattern compute units”, and replacing “n+1 buffers” with “a plurality of pattern storage units”.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
“an array of reconfigurable units to provide …” in claim 1,
“a configuration module to provide …” in claim 1, and
“a compiler configured to …” in claims 1-6.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may:
(1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or
(2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, the phrase "such as" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
In claim 1, the claim recites “a compiler to generate a pipeline of a plurality of PCUs related to a dataflow graph, interleaved between a plurality of PMUs”. It is grammatically unclear which element (e.g., a compiler, a pipeline, PCUs, or a dataflow graph) are interleaved with PMUs. Independent claim 9 has the same issue.
Dependent claims 2-8 and 10-16 are rejected for the same reason as their preceding parent claim rejected.
In claim 13, “a PMU between one or more PCUs” is unclear, since the scope includes “a PMU between one PCU”.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description:
In fig. 3, reference numerals 337, 357, 378, 358, 379, 359, 351, 352, 353, 354, 355, 356, 360, 361, 364, 265, 368, 369, 391, 392 are not found in specification. The numeral 130 appeared to be incorrectly placed.
In fig. 4, reference numerals 450, 451, 452, 453, 454, 455 and 460 are not found in specification.
Applicant is advised to check formalities in all drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn (US 9,354,850) in view of Lin (7,406,588).
Referring to claims 1 and 9-10, Ahn discloses a system (fig.12, reconfigurable processor 90) comprising:
an array of reconfigurable units (fig. 12, coarse-grained reconfigurable architecture CGRA 970) and
a configuration module (fig. 12, modulo scheduler 910) to provide configuration data (16:22-35, hardware information, ISA information, instructions, schedules; fig. 12, configuration memory 920) to configure
a plurality of configurable elements (fig. 2, function units 0/1/2/3, pipeline registers 230 and register file 220 in CGRA 22) in the array of reconfigurable units such as pattern memory units PMUs (fig. 2, pipeline registers 230), pattern compute units PCUs (fig. 2, function units 0/1/2/3) and communication agents (fig. 2, busses connecting function units and pipeline registers),
a compiler (fig. 10, compiler 105) to generate (fig. 6A, compile) a pipeline (fig. 6A, pipeline 62, e.g., RF0->FU0->FU1->FU3->RF1->FU4) of a plurality of PCUs (fig. 6A, FU0/FU1/FU3/FU4 622/623/624/626) related to a dataflow graph (fig. 5, graph; fig. 6A, dependency graph 62; 7:53-67), interleaved between a plurality of PMUs (fig. 6A, RF0/RF1 interleaved between FU0/1/3/4).
Lin discloses each PCU (fig. 1, circuit 111) is coupled to perform calculation based on data received from a first PMU (fig. 1, register 120) of the plurality of PMUs (fig. 1, register 120/121/122/123) and store results of the calculations into a second PMU (fig. 1, register 121) of the plurality of PMUs after a latency (fig. 2, CK0/CK1 for data from register 120 to 121),
wherein the first PMU (fig. 1, register 120) is placed before the PCU (fig. 1, circuit 111) and the second PMU (fig. 1, register 121) is after the PCU in the pipeline, and
wherein the compiler is to remove (fig. 5, bypass register 221 with controller 232 enable 2341 CK1)
Ahn and Lin are analogous art because they are from the same field of endeavor in optimizing intermediate registers in pipelined processor. Before the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Ahn and Lin before him or her to modify the compiler for instruction scheduling of Ahn to include the register bypassing of Lin, thereafter the instructions are executed with registers bypassed between pipeline stages. The suggestion and/or motivation for doing so would be obtaining the advantage of reduced power consumption (2:52-56) as suggested by Lin. Therefore, it would have been obvious to combine Ahn with Lin to obtain the invention as specified in the instant application claims.
As to claims 2 and 11, Lin discloses the system of claim 1, wherein the compiler is to fuse a first PCU (fig. 6C, circuit 211) with a second PCU (fig. 6C, circuit 212) after removing an intermediate PMU (fig. 6D, register 221) to produce a pipeline (fig. 6D, pipeline) having a reduced number (fig. 6D, bypassed register 221) of PCUs and PMUs. (see TSM analysis above)
As to claim 3, Ahn discloses the system of claim 1, wherein the compiler is to estimate (fig. 14, inter-iteration dependency E15) the latency of each PCU (fig. 14, less latency from function units directly forward data E25).
As to claims 4 and 12, Lin discloses the system of claim 3, wherein the compiler is to identify a first PCU (fig. 6C, circuit 212) with a first latency (fig. 6C, CK0/CK1 220/221) and identify a second PCU (fig. 6C, circuit 211) having a second latency (fig. 6C, CK0 220) lower than the first latency (fig. 2, CK0 has lower latency than CK0/CK1). (see TSM analysis above)
As to claim 5, Lin discloses the system of claim 4, wherein the compiler is to remove a PMU (fig. 6D. register 221 bypassed) between the first PCU (fig. 6D, circuit 212) and the second PCU (fig. 6D, circuit 211). (see TSM analysis above)
As to claims 6 and 14, Ahn discloses the system of claim 5, wherein the compiler is to fuse the first PCU and the second PCU into a fused PCU (fig. 6A, ADD FU0 622/SHIFT FU1 623).
As to claim 7, Lin discloses the system of claim 1, wherein each PMU of the plurality of PMUs is divisible into an input portion (fig. 4, input before CK0) that receives data and an output portion (fig. 4, output after CK0) that provides data concurrent with the input portion receiving data. (see TSM analysis above)
As to claim 8, Ahn discloses the system of claim 7, wherein each PCU of the plurality of PCUs is to perform calculations (fig. 6A, ADD FU0 622) based on data from the output portion of a preceding PMU (fig. 6A, register RF0 621) and store results of the calculations into the input portion of a following PMU (fig. 6A, register RF0 621 via 6221).
As to claim 13, Lin discloses the method of claim 12, comprising removing by the compiler, a PMU (fig. 6D, register 221) between PCUs (fig. 6D, circuits 211/212) having a combined latency (fig. 6D, CK0 required) lower than
As to claim 15, Ahn discloses the method of claim 9, wherein each PMU (fig. 6A, registers RF0 621/RF1 625) of the plurality of PMUs receives data and provides data concurrent with an input receiving data (fig. 6A, pipeline operations 62).
As to claim 16, Ahn discloses the method of claim 9, performing by each PCU of the plurality of PCUs, calculations (fig. 6A, ADD FU0 622) based on data from a preceding PMU (fig. 6A, register RF0 621) and storing results of the calculations into a following PMU (fig. 6A, register RF0 621 via 6221) of the plurality of PMUs of the pipeline.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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