Prosecution Insights
Last updated: October 22, 2026
Application No. 18/974,300

SENSE AMPLIFIER

Non-Final OA §DOUBLEPATENT
Filed
Dec 09, 2024
Priority
Feb 26, 2021 — divisional of 11/367,468 +2 more
Examiner
HO, HOAI V
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1036 granted / 1118 resolved
+32.7% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
19 currently pending
Career history
1137
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
30.2%
-9.8% vs TC avg
§102
45.0%
+5.0% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1118 resolved cases

Office Action

§DOUBLEPATENT
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. This office acknowledges receipt of the following item(s) from the Applicant: Information Disclosure Statement (IDS) was considered. 2. Claims 1-20 are pending in the application. Response to Election 3. Applicant's election without traverse of Species (claims) is acknowledged. Therefore, claims 1 and 3-16 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b) as being drawn to a non-elected invention. Double Patenting 4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b). Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 5. Claims 2 and 17-18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 and 6 of U.S. Patent No. 11783870. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows: Claims of the examined application are anticipated and the same scope of invention by claims of the reference such as a circuit comprising: a first transistor, wherein a source of the first transistor is connected to a first node, and wherein a drain of the first transistor is connected to a cell current source; a second transistor, wherein a source of the second transistor is connected to a second node, and wherein a drain of the second transistor is connected to a reference current source; a third transistor, wherein a source of the third transistor is connected to a supply voltage node, and wherein a drain of the third transistor is connected to the first node; a fourth transistor, wherein a source of the fourth transistor is connected to the supply node, and wherein a drain of the fourth transistor is connected to the second node; a first comparator, wherein a first input terminal of the first comparator is connected to the first node, and wherein a second input terminal of the first comparator is connected to the second node; and a second comparator wherein a first input terminal of the second comparator is connected to the first node, [[and]] wherein a second input terminal of second comparator is connected to the second node, wherein an output terminal of the second comparator is connected to the first comparator, and wherein the second comparator triggers the first comparator to compare a remaining voltage of the first node with a remaining voltage of the second node in response to at least one of the following: the remaining voltage of the first node is less than a reference voltage, and the remaining voltage of the second node is less than the reference voltage. Claims 19-20 are obvious to a claim 10 of the reference US Patent No. 11367468 (a parent case). 6. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs. 7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)). 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HOAI V HO/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Dec 09, 2024
Application Filed
Jul 11, 2025
Response after Non-Final Action
Oct 07, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
98%
With Interview (+5.5%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1118 resolved cases by this examiner. Grant probability derived from career allowance rate.

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