Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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2. Claims 1, 3-4, 17-23 and 27 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-3, 6-7, 9-10, 18-20 and 24 of US 12,167,651 B2 in view of Watanabe et al. (US 2015/0199936 A1, hereinafter referred as “Watanabe”).
18/974430 (Instant Application),
Claims # 1, 3-4, 17-23 and 27
US 12,167,651 B2,
Claims # 1-3, 6-7, 9-10, 18-20 and 24
1. A display device comprising: a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined; a first voltage line disposed on the substrate in the non-display area, wherein the first voltage line provides a first voltage to the pixels; a second voltage line disposed on the substrate in the non-display area, wherein the second voltage line provides a second voltage to the pixels; and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, wherein the first demux circuit area includes a plurality of first demux circuits and the second demux circuit area includes a plurality of second demux circuits, wherein the first demux circuits are connected to a first portion of a plurality of data lines transmitting data signals to the pixels, wherein the second demux circuits are connected to a second portion of the data lines, and wherein the first voltage line passes an area between the first demux circuit area and the second demux circuit area.
3. The display device of claim 1, wherein the display area has a circular shape.
4. The display device of claim 1, further comprising: a first voltage bypass line connected to the first voltage line and disposed along an edge of the display area, wherein the first voltage bypass line is electrically connected between the pixels and the first voltage line.
17. The display device of claim 1, wherein the first demux circuit area is disposed to be spaced apart fromthe second demux circuit area.
18. The display device of claim 1, further comprising: a third voltage line disposed on the substrate in the non-display area, wherein the third voltage line provides a third voltage to the pixels, wherein the third voltage is a high power supply voltage higher than an initialization voltage.
19. The display device of claim 18, wherein a part of the third voltage line passes the area between the first demux circuit area and the second demux circuit area.
20. The display device of claim 19, wherein a width of the part of the third voltage line is narrower than a width of another part of the third voltage line connected to the part.
21. The display device of claim 1, further comprising: a plurality of first data input lines connected to the first demux circuits; and a plurality of second data input lines connected to the second demux circuits, wherein a first data signal is applied to the first demux circuits through the first data input lines, and wherein a second data signal is applied through a second data input lines.
22. The display device of claim 21, wherein the first data input lines and the second data input lines are disposed in a same layer as each other.
23. The display device of claim 21, wherein the first data input lines and the second data input lines are disposed in different layers from each other.
27. The display device of claim 1, wherein the first voltage line includes a first part disposed between the first demux circuit area and the second demux circuit area, and a second part connected to the first part, and a width of the first part is narrower than a width of the second part.
1. A display device comprising: a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined; a first voltage line disposed on the substrate in the non-display area, wherein the first voltage line provides a first voltage to the pixels; a second voltage line disposed on the substrate in the non-display area, wherein the second voltage line provides a second voltage to the pixels; and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, wherein the first demux circuit area and the second demux circuit area transmit data signals to the pixels, and wherein the first voltage line passes an area between the first demux circuit area and the second demux circuit area.
2. The display device of claim 1, wherein the display area has a circular shape.
3. The display device of claim 1, further comprising: a first voltage bypass line connected to the first voltage line and disposed along an edge of the display area; and a second voltage bypass line connected to the second voltage line and disposed along the edge of the display area.
6. The display device of claim 1, wherein the first demux circuit area and the second demux circuit area are disposed to be spaced apart in one direction.
7. The display device of claim 1, further comprising: a third voltage line disposed on the substrate in the non-display area, wherein the third voltage line provides a third voltage to the pixels.
9. The display device of claim 7, wherein a part of the third voltage line passes the area between the first demux circuit area and the second demux circuit area.
10. The display device of claim 9, wherein a width of the part of the third voltage line is narrower than a width of another part of the third voltage line connected to the part.
18. The display device of claim 1, wherein the first demux circuit area includes a first demux circuit to which a first data signal is applied through a first data input line, and the second demux circuit area includes a second demux circuit to which a second data signal is applied through a second data input line.
19. The display device of claim 18, wherein the first data input line and the second data input line are disposed in a same layer as each other.
20. The display device of claim 18, wherein the first data input line and the second data input line are disposed in different layers from each other.
24. The display device of claim 1, wherein the first voltage line includes a first part disposed between the first demux circuit area and the second demux circuit area, and a second part connected to the first part, and a width of the first part is narrower than a width of the second part.
Although the conflicting claims are not identical, they are not patentably distinct from each other because limitations in claim 1 of the instant application read on limitations of claim 1 of US 12,167,651 B2. The claimed limitations recited in the present application are transparently found in the US 12,167,651 B2 with obvious wording variations.
US 12,167,651 B2 does not disclose wherein the first demux circuits are connected to a first portion of a plurality of data lines transmitting data signals to the pixels, wherein the second demux circuits are connected to a second portion of the data lines.
However, the examiner maintains that it was well known in the art to provide wherein the first demux circuits (104) are connected to a first portion of a plurality of data lines transmitting data signals to the pixels (Fig. 1 and ¶0025 discloses first de-multiplexer 104 has a first de-multiplex ratio, and is adapted to output the first data signal Din1 received from the controller 102 to a plurality of data buses DB), wherein the second demux circuits (106) are connected to a second portion of the data lines (Fig.1 and ¶0026 discloses second de-multiplexer 106 has a second de-multiplex ratio, and is adapted to output the second data signal Din2 received from the controller 102 to a plurality of data buses DB), as taught by Watanabe.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify US 12,167,651 B2 by specifically providing first and second demux circuits, as taught by Watanabe, for the purpose of providing a display device with de-multiplexers having different de-multiplex ratios (¶0001).
3. Claim 2 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 12,167,651 B2 in view of Watanabe and in further view of Hyeon et al. (US 2019/0140036 A1, hereinafter referred as “Hyeon”).
US 12,167,651 B2 does not disclose wherein a first distance between the first demux circuit area and the second demux circuit area is longer than a second distance between adjacent ones of the first demux circuits.
However, the examiner maintains that it was well known in the art to provide wherein a first distance between the first demux circuit area (DMUX2) and the second demux circuit area (DMUX1) is longer than a second distance between adjacent ones of the first demux circuits (DMUX2) (Figs. 8A-8C illustrate distance between the DMUX2 and DMUX1 is greater than the distance between adjacent DMUX1), as taught by Hyeon.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to further modify US 12,167,651 B2 so that as the bezels of display devices become slimmer, less space is available to dispose such wires, lines (¶0003).
Allowable Subject Matter
4. Claims 5-16 and 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on 5712727671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2621