DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 5/4/2026,
IDS filed on 6/4/2026.
Withdrawn objections and rejections
The specification objection has been withdrawn.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 8-9, 11-13, 15-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2025/0291756), in view of Ostby (U.S. 2019/0294439), in view of Official Notice.
As per claim 1:
Liu disclosed one or more processors comprising:
circuitry to perform at least one tensor instruction of a thread concurrently with one or more other instructions based, at least in part, on one or more indicators of the at least one tensor instruction being asynchronous (Liu: Figures 27-28 elements 2701, 2702A-D, 2708, and 2712, paragraphs 44, 46, 75, 83, 97-98, 335-338, 340-342, and 344)(The graphics cores (i.e. circuitry) simultaneously executes asynchronous matrix multiply and accumulate (MMA) operations (i.e. tensor instruction) with other barrier and load/store operations. Additionally, each individual graphics cores performs SIMT processing (i.e. instructions of a thread), which allows for concurrent instruction execution. Official notice is given that instructions include opcodes for the advantage of allowing decoders the ability to detect the operation type. Thus, it would have been obvious to one of ordinary skill in the art to implement an opcode with at least the asynchronous MMA operation to indicate the operation type and that the operation is performed asynchronously.).
Liu failed to teach wherein the one or more other instructions are subsequent to the at least one tensor instruction in the thread.
However, Ostby combined with Liu disclosed wherein the one or more other instructions are subsequent to the at least one tensor instruction in the thread (Ostby: Paragraph 120)( Liu: Figures 27-28 elements 2701, 2702A-D, 2708, and 2712, paragraphs 44, 46, 75, 83, 97-98, 335-338, 340-342, and 344)(Liu disclosed SIMT processing and parallel processing in general, but doesn’t disclose parallel and concurrent execution of SIMT instructions. Ostby disclosed that thread group instructions can be scheduled in a superscalar manner for executing multiple thread group instructions simultaneously. The combination allows for superscalar processing of SIMT instructions in Liu. This allows for parallel processing of the asynchronous MMA operations with subsequent SIMT instructions.).
The advantage of superscalar processing is that multiple instructions can be executed in parallel for increased performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the superscalar thread group processing method of Ostby into the graphics cores of Liu for the above advantage.
As per claim 2:
Liu and Ostby disclosed the one or more processors of claim 1, wherein the at least one tensor instruction and the one or more other instructions are to be added to one or more operation processing queues by a single thread of a cooperative thread array (CTA) (Liu: Figures 27-28 elements 2702A-D, 2708, 2712, and 2806, paragraphs 335-338 and 344)(Official notice is given that processor cores include instruction queues to schedule ready operations out-of-order for the advantage of increased performance. Thus, it would have been obvious to one of ordinary skill in the art that instruction queues can be used for out-of-order instruction when issuing for execution ready instructions, including SIMT MMA operations in the graphics cores. The out-of-order processing of MMA operations is done on the graphics cores in a SIMT (e.g. CTA) fashion.).
As per claim 4:
Liu and Ostby disclosed the one or more processors of claim 1, wherein the at least one tensor instruction and the one or more other instructions are to be performed by at least one of a processing core or an MMA accelerator of a graphics processing unit (GPU) independently from an order in which the at least one tensor instruction or the one or more other instructions are submitted (Liu: Figures 27-28 elements 2702A-D, 2708, 2712, and 2806, paragraphs 335-338 and 344)(Official notice is given that processor cores include instruction queues to schedule ready operations out-of-order for the advantage of increased performance. Thus, it would have been obvious to one of ordinary skill in the art that instruction queues can be used for out-of-order instruction when issuing for execution ready instructions, including SIMT MMA operations in the graphics cores.).
As per claim 5:
Liu and Ostby disclosed the one or more processors of claim 1, wherein the at least one tensor instruction comprises an instruction to perform a matrix multiply-accumulate (MMA) operation (Liu: Figures 27-28 elements 2701, 2702A-D, 2708, and 2712, paragraphs 44, 46, 97-98, 335-338, 340-342, and 344)(The graphics cores execute asynchronous matrix multiply and accumulate (MMA) operations.)
As per claim 6:
Liu and Ostby disclosed the one or more processors of claim 1, wherein a single thread of a cooperative thread array is to wait on an indication that the at least one tensor instruction is complete and that one or more operands of the at least one tensor instruction is permitted to be accessed or modified (Liu: Figures 27, 33, and 35, elements 2702A-D, 3302, 3503, 3510, paragraphs 335-338, 369, and 375)(Producer and consumer threads implement barrier operations so that asynchronous processing results are correctly passed to consumer operations. Liu doesn’t explicitly state that asynchronous MMA operations can be dependent upon each other. Official notice is given that matrix operations can be dependent on each other for the advantage of further processing intermediate results. Thus, it would have been obvious to one of ordinary skill in the art to implement barrier operations for asynchronous MMA operations that are dependent upon each other. In view of the above official notice, the consumer MMA operation waits for a barrier phase complete indication prior to execution.).
As per claim 8:
Claim 8 essentially recites the same limitations of claim 1. Therefore, claim 8 is rejected for the same reasons as claim 1.
As per claim 9:
The additional limitation(s) of claim 9 basically recite the additional limitation(s) of claim 2. Therefore, claim 9 is rejected for the same reason(s) as claim 2.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 4. Therefore, claim 11 is rejected for the same reason(s) as claim 4.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 5. Therefore, claim 12 is rejected for the same reason(s) as claim 5.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 6. Therefore, claim 13 is rejected for the same reason(s) as claim 6.
As per claim 15:
Claim 15 essentially recites the same limitations of claim 1. Therefore, claim 15 is rejected for the same reasons as claim 1.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 2. Therefore, claim 16 is rejected for the same reason(s) as claim 2.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 4. Therefore, claim 18 is rejected for the same reason(s) as claim 4.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 6. Therefore, claim 19 is rejected for the same reason(s) as claim 6.
Claims 3, 7, 10, 14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2025/0291756), in view of Ostby (U.S. 2019/0294439), in view of Official Notice, further in view of Uberti (U.S. 12,361,262).
As per claim 3:
Liu and Ostby disclosed the one or more processors of claim 1.
Liu and Ostby failed to teach wherein the at least one tensor instruction comprises a plurality of instructions that are to be divided into a first stage and a second stage, and the circuitry is further to perform one or more wait instructions that cause the second stage to wait until an indication that the first stage is complete.
However, Uberti combined with Liu and Ostby disclosed wherein the at least one tensor instruction comprises a plurality of instructions that are to be divided into a first stage and a second stage, and the circuitry is further to perform one or more wait instructions that cause the second stage to wait until an indication that the first stage is complete (Uberti: Figures 1, 3, and 4 elements 110a-d, 302-306, 322-324 404, and 408, column 3 lines 46-57, column 6 lines 47-65, column 12 lines 14-55, column 13 lines 22-55, column 15 lines 52-62, and column 16 lines 23-35)(Liu: Figures 27-28 elements 2701, 2702A-D, 2708, and 2712, paragraphs 44, 46, 97-98, 335-338, 340-342, and 344)(Liu disclosed graphics cores that simultaneously execute asynchronous matrix multiply and accumulate (MMA) operations (i.e. tensor instruction) with other barrier and load/store operations. Uberti disclosed breaking larger tensor operations into smaller operations performed in parallel across computing units. Uberti also disclosed the tensor operations being performed in stages where intermediate results are further processed by subsequent tensor operations. The combination implements the tensor operations of Uberti using asynchronous MMA operations and barrier operations in Liu. The first tensor operations performed in parallel that generate first intermediate data reads upon the first stage operations. The second tensor operations performed in parallel that use the first intermediate data as inputs reads upon the second stage. The combination uses the barrier instructions to synchronize parallel execution such that second tensor operations aren’t performed until the first intermediate data and third tensor input data are ready for processing.).
The advantage of splitting large tensors into smaller sizes is that they can be assigned to multiple processing devices for parallel execution, which results in increased performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the tensor splitting methods of Uberti into Liu using the asynchronous MMA and barrier operations of Liu for the above advantage.
As per claim 7:
Liu and Ostby disclosed the one or more processors of claim 1.
Liu and Ostby failed to teach wherein the at least one tensor instruction comprises a plurality of instructions that are to be divided into a first stage and a second stage, and one or more instructions of the first stage are to be performed while the one or more other instructions modify instructions of the second stage.
However, Uberti combined with Liu and Ostby disclosed wherein the at least one tensor instruction comprises a plurality of instructions that are to be divided into a first stage and a second stage, and one or more instructions of the first stage are to be performed while the one or more other instructions modify instructions of the second stage (Uberti: Figures 1, 3, and 4 elements 110a-d, 302-306, 322-324 404, and 408, column 3 lines 46-57, column 6 lines 47-65, column 12 lines 14-55, column 13 lines 22-55, column 15 lines 52-62, and column 16 lines 23-35)(Liu: Figures 27-28 elements 2701, 2702A-D, 2708, and 2712, paragraphs 44, 46, 97-98, 335-338, 340-342, and 344)(Liu disclosed graphics cores that simultaneously execute asynchronous matrix multiply and accumulate (MMA) operations (i.e. tensor instruction) with other barrier and load/store operations. Uberti disclosed breaking larger tensor operations into smaller operations performed in parallel across computing units. Uberti also disclosed the tensor operations being performed in stages where intermediate results are further processed by subsequent tensor operations. The combination implements the tensor operations of Uberti using asynchronous MMA operations and barrier operations in Liu. The first tensor operations performed in parallel that generate first intermediate data reads upon the first stage operations. The second tensor operations performed in parallel that use the first intermediate data as inputs reads upon the second stage. The combination uses the barrier instructions to synchronize parallel execution such that second tensor operations aren’t performed until the first intermediate data and third tensor input data are ready for processing. The first tensor operations of the first stage modify inputs of the subsequent tensor operations of the second stage.).
The advantage of splitting large tensors into smaller sizes is that they can be assigned to multiple processing devices for parallel execution, which results in increased performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the tensor splitting methods of Uberti into Liu using the asynchronous MMA and barrier operations of Liu for the above advantage.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 3. Therefore, claim 10 is rejected for the same reason(s) as claim 3.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 7. Therefore, claim 14 is rejected for the same reason(s) as claim 7.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 3. Therefore, claim 17 is rejected for the same reason(s) as claim 3.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 7. Therefore, claim 20 is rejected for the same reason(s) as claim 7.
Response to Arguments
The arguments presented by Applicant in the response, received on 5/4/2026 are partially considered persuasive.
Applicant argues regarding claims 1, 8, and 15:
“Liu teaches a graphics processor with a plurality of processing elements and a memory to store a plurality of addressable multi-phase memory barriers. See Liu, [abstract]. Specifically, Liu teaches a barrier synchronization mechanism to synchronize asynchronous tensor transfers. See Liu, para. [0087.] However, while Liu teaches synchronizing asynchronous tensor transfer, the reference does not teach performing a "tensor instruction of a thread concurrently with one or more other instructions" (e.g., a non-tensor instruction) (emphasis added.).”
This argument is not found to be persuasive for the following reason. The claimed “other instruction” can be any other type of instruction, including tensor instructions. The claims include no recitations that limit the other instruction to being a non-tensor instruction.
Applicant argues regarding claims 1, 8, and 15:
“Furthermore, Liu fails to disclose a tensor instruction of a thread with one or more other instructions, "wherein the one or more other instructions are subsequent to the at least one tensor instruction in the thread." While Liu teaches that a large number of threads can be executed concurrently (See Liu, para. [0059]), the reference fails to teach that the one or more other instructions are performed concurrently with the at least one tensor instruction, even though the one or more other instructions are submitted subsequent to the at least one tensor instruction.”
This argument is found to be persuasive for the following reason. The examiner agrees that Liu failed to teach the newly claimed limitation. However, a new ground of rejection has been given due to the amendment.
Applicant argues regarding official notice:
“With regard to the Office's reliance on official notice, M.P.E.P. § 2144.03 recites: "Official notice unsupported by documentary evidence may be taken by the examiner where the facts asserted to be well-known, or to be common knowledge in the art, are 'capable of such instant and unquestionable demonstration as to defy dispute.' [...] It would not be appropriate for the examiner to take official notice of facts without citing a prior art reference where the facts asserted to be well known are not beyond dispute, or are not capable of instant and unquestionable demonstration as being well-known."
Applicant respectfully traverses the Office's use of official notice and submits that "one or more indicators of the at least one tensor instruction being asynchronous" is not well-known so as to be "capable of such instant and unquestionable demonstration as to defy dispute." Specifically, asynchronous tensor instructions are not capable of instant and unquestionable demonstration at least because tensor instructions are usually synchronous, instead of asynchronous. Furthermore, it is not capable of instant and unquestionable demonstration to perform a tensor instruction and another instruction (such as a non-tensor instruction) concurrently because of an indication that the tensor instruction is an asynchronous tensor instruction. Accordingly, Applicant submits that the assertion is not properly based on common knowledge and respectfully requests that adequate documentary evidence be provided in the next Office Action if the rejection is to be maintained.”
This argument is not found to be persuasive for the following reason. MPEP 2144.03 C states “To adequately traverse such a finding, an applicant must specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art … A general allegation that the claims define a patentable invention without any reference to the examiner’s assertion of official notice would be inadequate.” Applicant’s response hasn’t included why the noticed fact isn’t considered well-known in the art. Thus, the official notices taken are maintained.
In this instance, applicant stated that “asynchronous tensor instructions are not capable of instant and unquestionable demonstration …” This may or may not be the case, but is a moot point as the office action doesn’t take official notice regarding “asynchronous tensor instructions.” Instead, the office action takes official notice for instruction opcodes, instruction queues, and instruction dependencies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACOB PETRANEK/Primary Examiner, Art Unit 2183
Prosecution Insights