DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. In regard to applicant’s request, the last restriction requirement (5/13/26) is now withdrawn, and all pending claims 1-19 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1, 10 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (US 11,545,201).
Claims 1 & 10, Lai (Fig. 6A-6B) shows a resistive non-volatile memory comprising at least one gate-resistively-changeable field effect transistor (with gate = 618) with at least one of its source/drain terminals 614 electrically connected to at least one bit line terminal 608; and a unipolar source/channel/drain diode (102) implemented by a field effect transistor without a gate electrode, and two terminals 608 of the unipolar source/channel/drain diode being electrically connected to a source line SL and the at least one gate-resistively-changeable field effect transistor by the BL end, respectively. For example, Fig. 3 shows a multilayer stack 104 is formed by a unipolar S/D diode (without a gate), as seen as a PIN diode (with 302 = N-type and 306 = P-type).
Claim 15, Fig. 8B shows an operation which includes the step of applying a zero voltage (or ground = GND to SLn+2 terminal) to one of a bit line (BL) and a source line (SL), see memory cell 104 as example, and applying a nonzero voltage (or Vr > 0 to BLm+2 terminal) of another of the bit line and the source line to operate the resistive non-volatile memory, wherein the gate-resistively-changeable field effect transistor is electrically connected to the bit line, the unipolar source/channel/drain diode is implemented by a field effect transistor without a gate electrode, two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the gate-resistively-changeable field effect transistor respectively.
3. Claims 1 & 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al (US 2022/0199622).
Claims 1 & 10, Lai (Fig. 4-5A) shows a resistive non-volatile memory comprising at least one gate-resistively-changeable field effect transistor (with gate = T1) with at least one of its source/drain terminals electrically connected to at least one bit line terminal BL1; and a unipolar source/channel/drain diode (102) implemented by a field effect transistor (T2) without a gate electrode, and two terminals of the unipolar source/channel/drain diode being electrically connected to a source line SL1 and the at least one gate-resistively-changeable field effect transistor by the BL1 end, respectively.
Allowable Subject Matter
4. Claims 2-9, 11-14 & 16-20 are objected as being dependent on the rejected
claims above, but they tentatively contain other allowable subjected matter over the prior arts of record as they recite additional novel limitations, which are not clearly suggested nor seen elsewhere at this time.
5, Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
Prosecution Insights