DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 18/974,824 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
IFORMATION CONCENING DRAWING:
3. Application’s drawing submitted on 12/10/2024 are acceptable for examination purposes.
IFORMATION CONCENING IDS:
4. The information disclosure statement (IDS) submitted on 112/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner. A copy (copies) of PTOL-1449s initialed and signed by the examiner is/are attached to the instant office action.
INFORMATION CONCERNING FOREIGN PRIORITY:
Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in Republic of Korea on O5/21/2024.
RELEVANT PRIOR ART CITED BY THE EXAMINER:
5. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure.
Knoth et al. (US 20220091649 A1) teaches “…determine a number of power credits to deduct based on a type of operation being performed…” (par. 0019).
MUKKER et al. (US 20210109587 A1) teaches “…The power management circuitry 204 can also actively move power budget from one component to another in the solid state drive 102 until a threshold of cumulative activity has been reached or exceeded.…” (par. 0036).
Sistla et al. (US 20120185706 A1) teaches “…power credit may be accumulated and later spent when a consumption amount over the limit is required by the power domain…” (par. 0044).
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hatch et al. “Hatch” (US 2020/0409441 A1) in view of Margetts et al. “Margetts”.
6. Regarding claim 1, Hatch teaches or suggests:
A data storage device (e.g., Fig. 1A) comprising: a plurality of memory dies;” (e.g., ¶ 0034, Dies 300 in Fig. 1D).
“a command storage configured to store commands;” (e.g., Fig. 1C, ¶ 0051, interfaces 228/258 may contain one or more command queues. These command queues may contain read, write, and erase commands).
“a credit information generator configured to generate and store maximum credit information indicating, for each command type, a maximum number of commands that are capable of being (e.g., Fig. 3, ¶ 0047, power control block 402 outputs power credits in order to regulate power usage; ¶ 0050, the information stored for each type of command includes an average power credit value and a peak power credit value). Peak power credit value represents maximum credit information recited in the claim.
“and a performance manager configured to provide the commands to the plurality of memory dies to process a number of commands less than or equal to the maximum credit information.” (e.g., Fig. 3, ¶ 0051, the interfaces 228/258 may delay the sending of commands to the memory packages 104 until there are sufficient power credit in view of the power credit usage per command type information 424). However, Hatch does not appear to expressly teach while Margetts discloses:
“maximum number of commands that are capable of being simultaneously performed by the plurality of memory dies” (e.g., ¶ 0051, the controller is able to schedule phases of the commands to be executed simultaneously within the present power budget). When cumulated power consumption exceeds the present power budget (e.g., credits), the commands could not be executed.
Disclosures by Hatch and Margetts are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the Integrated Power and Thermal Management in Non-volatile Memory disclosed by Hatch to include simultaneous execution commands if the power consumption does not exceed power budget (e.g., power credit).
The motivation for including the simultaneous execution of commands as taught by paragraph [0061] of Marggetts is to improve the estimation of the amount of energy consumption.
Therefore, it would have been obvious to combine teaching of Margetts with Hatch to obtain the invention as specified in the claim.
7. Regarding claim 15, Hatch teaches or suggests:
“A data storage device (e.g., Fig. 1A) comprising: a plurality of memory dies;” (e.g., ¶ 0034, Dies 300 in Fig. 1D).
“a command storage configured to store commands;” (e.g., Fig. 1C, ¶ 0051, interfaces 228/258 may contain one or more command queues. These command queues may contain read, write, and erase commands).
a credit information generator configured to store first maximum credit information indicating a maximum number of commands that are capable of being (e.g., Fig. 3, ¶ 0047, power control block 402 outputs power credits in order to regulate power usage; ¶ 0050, the information stored for each type of command includes an average power credit value and a peak power credit value). Peak power credit value represents maximum credit information recited in the claim.
“and second maximum credit information less than the first maximum credit information;” (e.g., Fig. 5, ¶ 0062, when thermal throttling is not in effect. The power control block 402 responds by reducing the size of the credit pool).
“and a performance manager configured to provide the commands to the plurality of memory dies based on one of the first maximum credit information and the second maximum credit information depending on a temperature of each of the plurality of memory dies.” (e.g., ¶ 0051, the controller is able to schedule phases of the commands to be executed simultaneously within the present power budget; ¶ 0043). When cumulated power consumption exceeds the present power budget (e.g., credits), the commands could not be executed. The memory controller adjust the thermal effect of temperature by reducing power budget (e.g., power credit) so that a lower number of commands are transmitted for execution. However, Hatch does not appear to expressly teach while Margetts discloses:
“maximum number of commands that are capable of being simultaneously performed by the plurality of memory dies” (e.g., ¶ 0051, the controller is able to schedule phases of the commands to be executed simultaneously within the present power budget; ¶ 0043). When cumulated power consumption exceeds the present power budget (e.g., credits), the commands could not be executed. The memory controller adjust Power budget caused by change in the temperature. The motivation for combining is based on the same rational presented for rejection of the independent claim 1.
8. Regarding claim 20, Hatch teaches or suggests:
“A controller comprising: a host interface configured to communicate with a host;” (e.g., Fig. 1A, ¶ 0026, Storage device 100 comprises a Controller 102…Storage device 100 comprises a Controller 102).
“a memory interface configured to communicate with a memory device;” (e.g., Fig. 1C, ¶ 0029). Fig. 1C shows back end processor (BEP) 112 communicate with memory packages (e.g., dies) via TM interfaces.
“and a processor configured to control the host interface and the memory interface,” (e.g., Fig. 1A, ¶ 0024, Controller 102 comprises a Front End Processor Circuit (FEP) 110 and one or more Back End Processor Circuits (BEP) 112). The storage device 100 comprises a controller 102. The controller includes a frond end processor is configured to communicate with the host via PCIe interface 130. The controller 102 also have a back end processor 112 configured to interface to memory packages 104.
“wherein the processor is configured to: generate a plurality of commands, each command corresponding to a request received from the host,” (e.g., Fig. 1C, ¶ 0051, with reference to FIG. 1C, interfaces 228/258 may contain one or more command queues. These command queues may contain read, write, and erase commands). Fig. 1C shows BEP 112 interfaces to FEP via PCIe interface 200, and to memory packages via interfaces 228 and 258. Fig. 3 shows memory controller 102 comprising the FEP 110, which include the control blocks such as power control 402 for generating Power credits. The controller 102 also includes BEP 112 including the execution module 422 configures to send the command to memory packages (e.g., dies) based on the power credits.
“and control the memory interface to provide the generated commands to the memory device based on maximum credit information indicating a number of commands that are capable of being (e.g., Fig. 1C and 3, ¶¶ 0050-0051). Generating and sending command to memory dies based on average and peak power credit values. However, Hatch does not appear to expressly teach while Margetts discloses:
“maximum number of commands that are capable of being simultaneously performed by the plurality of memory dies” (e.g., ¶ 0051, the controller is able to schedule phases of the commands to be executed simultaneously within the present power budget; ¶ 0043). When cumulated power consumption exceeds the present power budget (e.g., credits), the commands could not be executed. The memory controller adjust Power budget caused by change in the temperature. The motivation for combining is based on the same rational presented for rejection of the independent claim 1.
9. Regarding claim 9, Hatch further teaches:
“wherein the credit information generator generates the maximum credit information to include first maximum credit information and second maximum credit information having a value less than a value of the first maximum credit information.” (e.g., Fig. 5, ¶ 0062, when thermal throttling is not in effect. The power control block 402 responds by reducing the size of the credit pool).
Allowable Subject Matter
Claims 2-8, 10-14, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
DIRECTION OF FUTURE CORRESPENDENCES:
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
15. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138