DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dusmez (US 20200112243) in view of Standeven et al. (US 3461314) in further view of Koo et al. (US 20070272948).
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With respect to claim 1,Dusmez (US 20200112243) figure discloses an electronic component comprising: a base; a first semiconductor device attached to the base and including: a first Gallium nitride (GaN)-based (see [0027]) switch (1050) having a first gate (1054), a first source and a first drain (at 1056), wherein the first gate is arranged to control a current flow between the first source and the first drain; a second GaN-based switch (1052) having a second source (ground), a second gate (1054) and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain (at 1054); a second semiconductor device (1041) attached to the base and including: a logic circuit (1001) coupled to the second source (at ground) and arranged to detect a magnitude of the current flow (current flow through 1003); and a driver circuit (1003) coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches (1050 and 1052); and an electrically insulative encapsulant at least partially encapsulating the base, the first semiconductor device and the second semiconductor device (Here, this encapsulation is shown as the dotted line encapsulating the gate driver.) but fails to disclose wherein the first and second GaN-based switches are of the same conductivity type.
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It is well known in the art to create a inverter/gate driver of a single type of transistor (See Standeven (US 3461314)) disclosing a single type inverter.
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See also fig. 1A and 1B of Koo et al. (US 20070272948) disclosing single type MOSFET inverter. It would have been obvious at the time the invention was made to use a single type inverter in place of a CMOS driver in Dusmez for the purpose of simplicity, low cost and faster switching stability and reliability.
With respect to claim 2, Dusmez discloses the electronic component of claim 1, further comprising a first external terminal (to Switch drain terminal) coupled to the first drain, a second external terminal coupled to the first source (5v-15v power source terminal), and a third external (Vin) terminal coupled to the logic circuit (1001), the third external terminal arranged to transmit a signal (1054) corresponding to the detected magnitude of the current flow.
With respect to claim 3, Dusmez discloses the electronic component of claim 1, further comprising a resistor (resistor) coupled to the second source (coupled to ground) and wherein the logic circuit detects a voltage drop across the resistor that is proportional to the magnitude of the current flow. (at ground input of the 1001).
With respect to claim 4, Dusmez disclose the electronic component of claim 3, wherein the resistor is disposed within the second semiconductor device (Within 1041).
With respect to claim 5, Dusmez discloses the electronic component of claim 1, wherein the driver circuit synchronously controls (via 1054) on and off states of the first and the second GaN-based switches.
With respect to claim 6, Dusmez discloses the electronic component of claim 2, wherein the electronic component further comprises a fourth external terminal (PWM 1003) coupled to the logic circuit (1001 at 104), wherein the fourth external terminal is arranged to receive pulse width modulated signals (PWM).
With respect to claim 7, Dusmez discloses the electronic component of claim 6, further comprising a fifth external terminal, the fifth external terminal arranged to receive a power supply (5v power supply).
With respect to claim 8, Dusmez discloses a electronic component comprising: a first semiconductor device (1042) including: a first Gallium nitride (GaN)-based switch (1050) having a first gate, a first source and a first drain, wherein the first gate is arranged to control a current flow between the first source and the first drain; a second GaN-based switch (1052) having a second source, a second gate and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain (at 1054); a second semiconductor device (1041) including: a driver circuit (i..e 1041) coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches; a logic circuit (1001) arranged to: detect a magnitude of the current flow via a first signal received from the second source (at ground); and control the driver circuit to turn off the first and second GaN-based switches when the detected magnitude of the current flow exceeds a threshold current value (Vin); and an electrically insulative encapsulant at least partially encapsulating the first semiconductor device and the second semiconductor device (implemented in a structure) ;a first external terminal disposed at an exterior surface of the electronic component and coupled to the first drain (to switch gate terminal) ; and a second external terminal disposed at the exterior surface of the electronic component and coupled to the first source (at 5v-15v power supply) but fails to disclose wherein the first and second GaN-based switches are of the same conductivity type.
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It is well known in the art to create a inverter/gate driver of a single type of transistor (See Standeven (US 3461314)) disclosing a single type inverter.
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See also fig. 1A and 1B of Koo et al. (US 20070272948) disclosing single type MOSFET inverter. It would have been obvious at the time the invention was made to use a single type inverter in place of a CMOS driver in Dusmez for the purpose of simplicity, low cost and faster switching stability and reliability.
With respect to claim 9, Dusmez discloses the electronic component of claim 8, wherein the electronic component further comprises a third external terminal coupled (Vin) to the logic circuit (1001), the third external terminal arranged to transmit (via output 1054) a signal corresponding to the detected magnitude of the current flow (current flow through 1003).
With respect to claim 10, Dusmez discloses the electronic component of claim 8, further comprising a resistor (resistor) coupled to the second source (at ground) and wherein the logic circuit (1001) detects a voltage drop across the resistor that is proportional to the magnitude of the current flow (detected at ground input of 1001).
With respect to claim 11, Dusmez discloses the electronic component of claim 10, wherein the resistor is disposed within the second semiconductor device (within 1041).
With respect to claim 12, Dusmez discloses the electronic component of claim 8, wherein the driver circuit synchronously controls (at 1054) on and off states of the first and the second GaN-based switches (1050 and 1052).
With respect to claim 13, Dusmez discloses the electronic component of claim 9, further comprising a fourth external terminal (at PWM 1003 input) coupled to the logic circuit (coupled at 1054), wherein the fourth external terminal is arranged to receive pulse width modulated signals (PWM signals).
With respect to claim 14, Dusmez discloses the electronic component of claim 13, further comprising a fifth external terminal (at 5v), the fifth external terminal arranged to receive a power supply.
With respect to claim 15, Dusmez discloses a method of operating an electronic component, the method comprising: receiving an input signal at a first external terminal (5v); transmitting the input signal to a driver circuit disposed on a first semiconductor device (1041) disposed within the electronic component, wherein the driver circuit transmits first and second drive signals in response to receiving the input signal (1054); transitioning a first Gallium nitride (GaN)-based switch (1050) between a first on state and a first off state in response to receiving the first drive signal, wherein the first GaN-based switch is disposed on a second semiconductor device (1042) disposed within the electronic component and wherein the first GaN-based switch controls a flow of a current between a second external terminal (5-15v) of the electronic component and a third external terminal (gnd) of the electronic component; transitioning a second Gallium nitride (GaN)-based switch (1052) between a second on state and a second off state in response to receiving the second drive signal, wherein the second GaN-based switch is disposed on the second semiconductor device (1042); detecting a magnitude of the current via a detection circuit disposed on the second semiconductor device, wherein the detection circuit is coupled to the second GaN-based switch; and generating an output signal at a fourth external terminal (to switch gate) , wherein the output signal corresponds to the magnitude of the current but fails to disclose wherein the first and second GaN-based switches are of the same conductivity type.
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It is well known in the art to create a inverter/gate driver of a single type of transistor (See Standeven (US 3461314)) disclosing a single type inverter.
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782
297
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Greyscale
See also fig. 1A and 1B of Koo et al. (US 20070272948) disclosing single type MOSFET inverter. It would have been obvious at the time the invention was made to use a single type inverter in place of a CMOS driver in Dusmez for the purpose of simplicity, low cost and faster switching stability and reliability.
With respect to claim 16, Dusmez discloses the method of claim 15, wherein the detection circuit comprises a resistor (resistor) disposed within the first semiconductor device (1041), the resistor being coupled to the fourth external terminal.
With respect to claim 17, Dusmez discloses the method of claim 15, the transitioning of the first and second GaN-based switches occurs synchronously. (Here, 1050 and 1052 have the same input thus the transitioning must occur synchronously. See fig. 10)
With respect to claim 18, Dusmez discloses the method of claim 15, further comprising providing power to the first semiconductor device via a fifth external terminal (5v).
With respect to claim 19, Dusmez discloses the method of claim 15, further comprising detecting a direction of the current via the detection circuit (1003).
With respect to claim 20, Dusmez discloses the method of claim 19, wherein the generated output signal (to switch gate) corresponds to the magnitude and the direction of the current.
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument that Dumez fails to disclose wherein the transistors are not GAN- based switches, the Examiner disagrees. In [0027], Dumez discloses “ High frequencies can be 1 MHz or more with GaN, which significantly improves power density while maintaining high efficiency. In addition to facilitating such high frequencies, the proposed approach reduces circulating current in high frequency applications.”, here it is thus interpreted as the high frequencies are made with galiumn nitride.
With respect to the same conductivity type, the Examiner points out that a gate driver of the same conductivity type is viewed as obvious in that it is well known to create a inverter/driver of the same conductivity type as disclosed in the aforementioned references.
With respect to applicant’s argument that the cited switches in the gate driver are not part of the power switch controlling current flow between the source and drain terminals for the main switching function, transistors in general control the flow of the current between the source and drain by virtue of them being on or off at the gate and thus the transistors in Dumez alone or Dumez in view of the cited references would meet this stipulation.
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 3/30/2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2836
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