CTNF 18/975,461 CTNF 91809 DETAILED ACTION This non-final action is responsive to the following communications: application filed on 12/10/2024. Claims 1-20 are pending. Claims 1, 15, and 20 are independent. Examiner Notes A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification . B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art , a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA 3. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement 4. IDS filed on 12/10/2024 has been considered. Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard. Specification Objections 5. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “Receiving circuit that improves the integrity of data signals in a semiconductor memory device” Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA 8. Claim s 1-2, 7, 15-16, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Palmer (US 2006/0132191 A1) . Regarding independent claim 1 , Palmer teaches a receiving circuit (Fig. 1: 100 “receiver” with equalization circuitry. See Examiner’s Markup of Palmer Figure 1. See also Fig. 1-Fig. 7 for illustrated components and functionality) comprising: PNG media_image1.png 443 640 media_image1.png Greyscale a first input transistor (Fig. 1: 115a) connected between a first common node (Fig. 1: CX) and a first output node (Fig. 1: srcN) and configured to receive a first input signal (Fig. 1: rxP) through a first input node (Fig. 1: IN1) ; a second input transistor (Fig. 1: 115b) connected between the first common node (Fig. 1: 115) and a second output node (Fig. 1: srcP) and configured to receive a second input signal (Fig. 1: rxN) through a second input node (Fig. 1: IN2) ; a first equalization transistor (Fig. 1: 120a) connected in parallel with the first input transistor (Fig. 1: 115a) ; a second equalization transistor (Fig. 1: 120b) connected in parallel with the second input transistor (Fig. 1: 115b) ; a filter circuit (Fig. 1: 125 “high-pass filter”, para [0013]) including one or more internal nodes (Fig. 1: eqP, eqN) and configured to filter the first input signal (para [0013], lines 16-21: removes frequency specific signal components from input signal. See also para [0014]) ; and an input capacitance adjustment circuit (Fig. 1: 135a, 140a, 135b, 140b, vcm source circuit) configured to adjust one or more voltage levels of the one or more internal nodes (Fig. 4: 410 signal amplitude level at eqP, eqN) based on an operating mode of a semiconductor memory device (Fig. 4: 405 based on operations defined by inputs rxP, rxN. For example, inputs rxP, rxN provided in receiver during sense or, read operation to sense amp of Fig. 3: 315) , the operating mode including a write mode or a read mode (e.g., selectively during read operation, amplification of rxP, rxN is performed and amplified signals ampP, ampN is provided to sense amplifier and such function is not present during write) . Regarding claim 2 , Palmer teaches the receiving circuit of claim 1, wherein the filter circuit includes: a first sub-filter circuit connected between the first input node and a first filter node; and a second sub-filter circuit connected between the second input node and the first filter node, and wherein the input capacitance adjustment circuit is configured to adjust a voltage level of the first filter node based on the operating mode of the semiconductor memory device. (See claim 20 rejection analysis since claim is substantially similar to claim 20 limitations) Regarding claim 7 , Palmer teaches the receiving circuit of claim 2, wherein the first sub-filter circuit includes: a first metal oxide semiconductor (MOS) capacitor connected between the first input node and a second filter node; and a first resistor connected between the second filter node and the first filter node. (See claim 20 rejection analysis since claim is substantially similar to claim 20 limitations) Regarding independent claim 15 , Palmer teaches a receiving circuit (Fig. 1: 100 “receiver” with equalization circuitry. See Examiner’s Markup of Palmer Figure 1. See also Fig. 1-Fig. 7 for illustrated components and functionality) comprising: a first input transistor (Fig. 1: 115a) connected between a first common node (Fig. 1: CX) and a first output node (Fig. 1: srcN) and configured to receive a first input signal (Fig. 1: rxP signal) through a first input node (Fig. 1: IN1) ; a second input transistor (Fig. 1: 115b) connected between the first common node (Fig. 1: CX) and a second output node (Fig. 1: srcP) and configured to receive a second input signal (Fig. 1: rxN signal) through a second input node (Fig. 1: IN2) ; an equalization circuit (Fig. 1: 120, 130, 125 combined) including one or more internal nodes (Fig. 1: eqP, eqN) and configured to equalize the first input signal (para [0015]: “equalization signals” eqP, eqN are generated and “amplified”. See also Fig. 4); and an input capacitance adjustment circuit (Fig. 1: 135a, 140a, 135b, 140b, vcm source circuit) configured to adjust one or more voltage levels of the one or more internal nodes (Fig. 4: 410 signal amplitude level at eqP, eqN) based on an operating mode of a semiconductor memory device (Fig. 4: 405 based on operations defined by inputs rxP, rxN. For example, inputs rxP, rxN provided in receiver during sense or, read operation to sense amp of Fig. 3: 315) , the operating mode including a write mode or a read mode (e.g., selectively during read operation, amplification of rxP, rxN is performed and amplified signals ampP, ampN is provided to sense amplifier and such function is not present during write) . Regarding claim 16 , Palmer teaches the receiving circuit of claim 15, wherein the equalization circuit includes: a first sub-filter circuit connected between the first input node and a first filter node, and wherein the input capacitance adjustment circuit is configured to adjust a voltage level of the first filter node based on the operating mode of the semiconductor memory device. (See claim 20 rejection analysis since claim is substantially similar to claim 20 limitations) Regarding independent claim 20 , Palmer teaches a receiving circuit (Fig. 1: 100 “receiver” with equalization circuitry. See Examiner’s Markup of Palmer Figure 1. See also Fig. 1-Fig. 7 for illustrated components and functionality) comprising: a first input transistor (Fig. 1: 115a) connected between a first common node (Fig. 1: CX) and a first output node (Fig. 1: srcN) and configured to receive a first input signal (Fig. 1: rxP signal) through a first input node (Fig. 1: IN1) ; a second input transistor (Fig. 1: 115b) connected between the first common node (Fig. 1: CX) and a second output node (Fig. 1: srcP) and configured to receive a second input signal (Fig. 1: rxN) through a second input node (Fig. 1: IN2) ; a first equalization transistor (Fig. 1: 120a) connected in parallel with the first input transistor (Fig. 1: 115a) ; a second equalization transistor (Fig. 1: 120b) connected in parallel with the second input transistor (Fig. 1: 115b) ; a filter circuit (Fig. 1: 125 “high-pass filter”, para [0013]) configured to filter the first input signal (para [0013], lines 16-21: removes frequency specific signal components from input signal. See also para [0014]) , the filter circuit (Fig. 1: 125) including a first filter node (Fig. 1: eqN) , a second filter node (Fig. 1: eqP) , and a third filter node (Fig. 1: vcm node) ; and an input capacitance adjustment circuit (Fig. 1: 135a, 140a, 135b, 140b, vcm source circuit) configured to adjust a voltage level of the first filter node (Fig. 1: eqP) and a voltage level of the second filter node (Fig. 1: eqP) based on an operating mode of a semiconductor memory device (Fig. 4: 405 based on operations defined by inputs rxP, rxN. For example, inputs rxP, rxN provided in receiver during sense or, read operation to sense amp of Fig. 3: 315) , the operating mode including a write mode or a read mode (e.g., selectively during read operation, amplification of rxP, rxN is performed and amplified signals ampP, ampN is provided to sense amplifier and such function is not present during write) , wherein the filter circuit (Fig. 1: 125) includes: a first sub-filter circuit (Fig. 1: 125a) connected between the first input node (Fig. 1: IN1) and the first filter node (Fig. 1: EqN) ; and a second sub-filter circuit (Fig. 1: 125b) connected between the second filter node (Fig. 1: eqP) and the first filter node (Fig. 1: eqN which is coupled to IN2) , and wherein the first sub-filter circuit includes: a first metal oxide semiconductor (MOS) capacitor (Fig. 1: 135a “capacitor” in context of para [0016], para [0029]: capacitor works in conjunction with MOS transistors integrated circuit and thus it cannot be discrete capacitor) connected between the first input node (Fig. 1: IN1) and a third filter node (Fig. 1: vcm node) ; and a first resistance network (Fig. 1: 140b) connected between the third filter node (Fig. 1: vcm node) and the first filter node (Fig. 1: eqN) and having a variable first composite resistance value (para [0016]: voltage-controlled resistances) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-6, 8-14, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims. Prior Art Not Relied Upon 07-96 The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Hong et al. (US 2020/0313638 A1): Fig. 2-Fig. 14 disclosure applicable for all claims. Teaches a receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal. Rogers (US 10,944,602 B1): Fig. 1-Fig. 6 disclosure applicable for all claims. It is suggested that applicant consider all prior arts made of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825 Application/Control Number: 18/975,461 Page 2 Art Unit: 2825 Application/Control Number: 18/975,461 Page 3 Art Unit: 2825 Application/Control Number: 18/975,461 Page 4 Art Unit: 2825 Application/Control Number: 18/975,461 Page 5 Art Unit: 2825 Application/Control Number: 18/975,461 Page 6 Art Unit: 2825 Application/Control Number: 18/975,461 Page 7 Art Unit: 2825 Application/Control Number: 18/975,461 Page 8 Art Unit: 2825 Application/Control Number: 18/975,461 Page 9 Art Unit: 2825 Application/Control Number: 18/975,461 Page 10 Art Unit: 2825 Application/Control Number: 18/975,461 Page 11 Art Unit: 2825
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