DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 07/29/2026 in which claims 1-7 are amended and claim 9 is added has been entered of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 2018/0025784) in view of Chan (US Pub. 2007/0171725).
Regarding claim 1, Fig. 2 and Fig. 8 of Lee discloses a method performed by a memory device including a first sub-block [one page of memory 100, Fig. 2] and a second sub-block [another page of memory 100, Fig. 2] programed in a state [can be any state], the method comprising:
performing a partial erase operation including erasing data stored in the first sub-block [as discloses in paragraph 0041, controller 200 perform partial erase operation for one of the page]; and
performing a partial program operation including reprogramming the first sub-block [as discloses in paragraph 0041, the same page that was partially erased earlier is programed] in the state in which the second sub-block is programmed [there are plurality of pages in the memory, and Fig. 8 of Lee discloses programming a whole page. Therefore, there is inherently a second page (block) that is programmed],
wherein performing the partial program operation includes:
applying a program voltage to a selected word line of the first sub-block [Fig. 8 shows how a program operation is performed including setting up programming voltage in step S82 and applying the programming voltage in step S85];
applying a verify voltage to the selected word line [verify step S86, Fig. 8].
Lee teaches applying a precharge voltage to the selected memory cell [as discloses in paragraph 0072, the memory cell is also precharged], but does not specifically disclose applying a pre-charge voltage to the selected word line. However, Fig. 16 of Chan discloses a memory programing operation including a step of applying a precharge voltage to the selected word line [step 720].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Chan’s memory operations to the teachings of Lee’s memory operations such that Lee memory operation includes applying pre-charge voltage to selected word line in a manner according to Chan’s teachings for the purpose of precision programming and saving time [paragraph 0145].
Regarding claim 2, Fig. 2 of Lee discloses wherein, a voltage at constant level is applied to word lines of the second sub-block [as discloses in paragraph 0074, a pulse voltage with increasing steps are applied to word line for programming. At each step, the voltage is constant] while applying the program voltage.
Regarding claim 3, Fig. 2 of Lee discloses wherein, a voltage [pass voltage] at level lower than the voltage of the program voltage is applied to an unselected word line of the first sub-block [as discloses in paragraph 0075, pass voltage is applied to un-selected word line. Pass voltage is lower than the programming voltage] while applying the program voltage.
Regarding claim 4, paragraph 0095 discloses wherein, a voltage having a level different from that of the verify voltage is applied to word lines of the second sub-block and an unselected word line of the first sub-block [as discloses in paragraph 0095, verify voltage Vf is applied during the verify operation. Vf is different from pass voltage] while applying the verify voltage.
Regarding claim 5, paragraph 0062 of Lee discloses wherein, the precharge voltage is applied to word lines of the first sub-block such that a channel of the first sub-block is boosted while applying the precharge voltage.
Regarding claim 6, paragraph 0075 discloses wherein, a level of a voltage applied to word lines of the second sub-block is maintained at a constant level such that memory cells included in the second sub-block are turned on [as discloses in paragraph 0075, a program voltage is applied to word line during precharge operation, at each step, the voltage applies to the word line is constant] while applying the precharge voltage.
Regarding claim 8, paragraph 0041 of Lee discloses wherein the partial program operation is performed in a direction from the first sub-block to the second sub-block [first page to second page].
Regarding claim 9, Lee discloses all claimed invention, but does not specifically disclose wherein the precharge voltage is applied to the selected word line to increase a voltage of the selected word line; and wherein the voltage of the selected word line decreases again while applying the precharge voltage. However, Fig. 17 of Chan discloses wherein the precharge voltage is applied to the selected word line [WL] to increase a voltage of the selected word line [voltage increases from WL to WH]; and wherein the voltage of the selected word line decreases again [after SCAN 4] while applying the precharge voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Chan’s memory operations to the teachings of Lee’s memory operations such that Lee memory operation includes applying pre-charge voltage to selected word line in a manner according to Chan’s teachings for the purpose of precision programming and saving time [paragraph 0145].
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art does not teach or suggest either alone or in combination wherein, a voltage having a level equal to or lower than the voltage obtained by adding a channel potential corresponding to a dummy word line and a threshold voltage of the dummy word line is applied to the dummy word line while applying the program voltage.
Response to Arguments
Applicant’s arguments with respect to claims 1-6 and 8-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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