Prosecution Insights
Last updated: August 18, 2026
Application No. 18/975,567

MEMORY DEVICE AND OPERATING METHOD THEREOF

Final Rejection §102
Filed
Dec 10, 2024
Priority
Apr 09, 2021 — RE 10-2021-0046788 +1 more
Examiner
TRAN, ANTHAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
642 granted / 775 resolved
+14.8% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
802
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 775 resolved cases

Office Action

§102
CTNF 18/975,567 CTNF 81308 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-6 and 8 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee (US Pub. 2018/0025784) . Regarding claim 1 , Fig. 2 and Fig. 8 of Lee discloses a method for operating a memory device including a first sub-block [one page of memory 100, Fig. 2] and a second sub-block [another page of memory 100, Fig. 2], the method comprising: performing a partial erase operation of erasing data stored in the first sub-block [as discloses in paragraph 0041, controller 200 perform partial erase operation for one of the page]; and performing a partial program operation of reprogramming the first sub-block [as discloses in paragraph 0041, the same page that was partially erased earlier is programed] in a state in which the second sub-block is programmed [there are plurality of pages in the memory, and Fig. 8 of Lee discloses programming a whole page. Therefore, there is inherently a second page (block) that is programmed], wherein the performing of the partial program operation includes: a program step of applying a program voltage to a selected word line of the first sub-block [Fig. 8 shows how a program operation is performed including setting up programming voltage in step S82 and applying the programming voltage in step S85]; a verify step of applying a verify voltage to the selected word line [verify step S86, Fig. 8]; and a precharge step of applying a precharge voltage to the selected word line [as discloses in paragraph 0072, the memory cell is also precharged]. Regarding claim 2 , Fig. 2 of Lee discloses wherein, in the program step, a voltage having a constant level is applied to word lines of the second sub-block [as discloses in paragraph 0074, a pulse voltage with increasing steps are applied to word line for programming. At each step, the voltage is constant]. Regarding claim 3 , Fig. 2 of Lee discloses wherein, in the program step, a voltage [pass voltage] having a level lower than that of the program voltage is applied to an unselected word line of the first sub-block [as discloses in paragraph 0075, pass voltage is applied to un-selected word line. Pass voltage is lower than the programming voltage]. Regarding claim 4 , paragraph 0095 discloses wherein, in the verify step, a voltage having a level different from that of the verify voltage is applied to word lines of the second sub-block and an unselected word line of the first sub-block [as discloses in paragraph 0095, verify voltage Vf is applied during the verify operation. Vf is different from pass voltage]. Regarding claim 5 , paragraph 0062 of Lee discloses wherein, in the precharge step, the precharge voltage is applied to word lines of the first sub-block such that a channel of the first sub-block is boosted. Regarding claim 6 , paragraph 0075 discloses wherein, in the precharge step, a level of a voltage applied to word lines of the second sub-block is maintained at a constant level such that memory cells included in the second sub-block are turned on [as discloses in paragraph 0075, a program voltage is applied to word line during precharge operation, at each step, the voltage applies to the word line is constant]. Regarding claim 8 , paragraph 0041 of Lee discloses wherein the partial program operation is performed in a direction from the first sub-block to the second sub-block [first page to second page] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7 , the prior art does not teach or suggest either alone or in combination wherein, in the program step, a voltage having a level equal to or lower than that obtained by adding a channel potential corresponding to a dummy word line and a threshold voltage of the dummy word line is applied to the dummy word line . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825 Application/Control Number: 18/975,567 Page 2 Art Unit: 2825 Application/Control Number: 18/975,567 Page 3 Art Unit: 2825 Application/Control Number: 18/975,567 Page 4 Art Unit: 2825 Application/Control Number: 18/975,567 Page 5 Art Unit: 2825 Application/Control Number: 18/975,567 Page 6 Art Unit: 2825
Read full office action

Prosecution Timeline

Dec 10, 2024
Application Filed
Apr 30, 2026
Non-Final Rejection mailed — §102
Jul 22, 2026
Applicant Interview (Telephonic)
Jul 29, 2026
Response Filed
Jul 30, 2026
Examiner Interview Summary
Aug 17, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12706133
DYNAMIC MEMORY WITH LONG RETENTION TIME
2y 11m to grant Granted Aug 11, 2026
Patent 12700452
MEMORY DEVICE WITH IMPROVED DRIVER OPERATION AND METHODS TO OPERATE THE MEMORY DEVICE
2y 3m to grant Granted Aug 04, 2026
Patent 12694279
PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
4y 0m to grant Granted Jul 28, 2026
Patent 12688901
SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD LINES AND BIT LINES AND TEST METHOD FOR THE SAME
2y 2m to grant Granted Jul 21, 2026
Patent 12676180
MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME
2y 0m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.5%)
2y 3m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 775 resolved cases by this examiner. Grant probability derived from career allowance rate.

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