DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the host is configured to: determine the first portion of memory cells and the second portion of memory cells together as a total portion of memory cells; and the command indicates to store the first LBA as a starting LBA of the total portion in the register and the range of LBAs of the total portion in the second register.
Claim(s) 20 depends from claim 20 and as such is also objected for the same reason.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The method claim requires, in brief and saliently, accessing a first register in a previously introduced memory device. The method claim then requires that the first register is configured to store a first logical block address (LBA); this is followed by “at which the first data is stored in the memory device.” Given that the first register stores the address, interpretation of the “at which the first data is stored in the memory device,” in a way that is only fair to the present Application, is all over place: if the register stores the address, as claimed, can it also store the claimed first data? Or, is it claimed that somehow the LBA stores the first data. This latter interpretation follows directly from the claim: “the first register is configured to store a first logical block address (LBA) at which the first data is stored in the memory device.” That is, the register stores the address and it stores the data. Yet, this interpretation has not been found to have support in the specification/drawings of the instant Application. However, should this interpretation have support in said specification/drawings, it would be opportune this support be highlighted. Moreover, the last paragraph of the claim further introduces grounds of indefiniteness: “performing a refresh operation to refresh the first data at the first LBA” (emphasis added). It would seem the claimed data resides at the LBA. As found in MPEP 2173.06 (II), speculative interpretation about the meaning and terms employed in a claim or assumptions made as to the scope of the claim should not be part of the Application examination. The claim as a whole is found indefinite.
Claim(s) 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is believed that the MPEP may provide guidance that an Application can disclose multiple inventions, but the claims are generally not supposed to claim two independent and distinct inventions in the same claim. The present claim does just that. The apparatus of the claim is claimed to comprise, in brief and saliently: (A) a memory device comprising an array of cells which comprise at least two registers; one of which registers stores an LBA, and a second register stores a range of LBAs (Incidentally, and very importantly, the present claim stands alone, regardless of any other independent claim; and LBA is not defined);
a processing device to access the registers to locate the first LBA and range of LBAs;
said processing device to receive a refresh command to perform a refresh operation; and initiate said refresh operation.
It is thus clear that the accessing of the registers to locate the LBAs is completely divorced, standing alone and independently, from receiving a refresh command to perform a refresh operation. One does not cooperatively work with the other, and vice-versa. At the very least there could be grounds for restriction. As found in MPEP 2173.06 (II), speculative interpretation about the meaning and terms employed in a claim or assumptions made as to the scope of the claim should not be part of the Application examination. The claim as a whole is found indefinite.
Claim(s) 2-8 and 10-14 depend from claim(s) 1 and 9 and as such are therefore rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20240144988 to Seo et al. (“Seo”).
As to claim 15, Seo teaches A system (As found in at least FIG. 9: 3000), comprising: a host (As found in at least the abstract); a memory system comprising: a memory device comprising an array and in communication with the host (As found in at least FIG. 1: 100; and at least [0039]), the array comprising at least two registers (As found in at least FIG. 2, 100 comprises at least two registers: 106 and 108); and a processing device coupled to the memory device (As found in at least FIG. 1: processing device 200); wherein: the host is configured to: determine a first portion of memory cells of the memory device to be refreshed (As found in at least the Abstract); and send a command to store a first logical block address (LBA) associated with the portion of memory cells in a first of the at least two registers of the array (As found in at least FIG. 1: Auto refresh command; and as found in at least FIG. 2, the address is stored in one of 106 and 108); and the processing device is configured to: receive the command from the host; and store the first LBA in the register (As found in at least [0039] processing device 200 between host and memory device 100; as found in at least the Abstract, a command is received from the host, and as found in at least FIGS. 1-2, processing device 200 stores address in at least one of 106 and 108).
As to claim 16, Seo teaches the host is configured to send a refresh command to the memory device indicating to perform a refresh operation (As found in at least the Abstract).
As to claim 17-18, Seo teaches wherein the memory device is configured to, in response to receiving the refresh command: access the first register to obtain the first LBA; and refresh the first portion of memory cells in the array associated with the first LBA (As found in at least [0005]); determine a second portion of memory cells of the memory device to be refreshed; and send a second command to store a range of LBAs associated with the second portion of memory cells in a second of the at least two registers of the array (As found in at least Claim 1, one of 106 and 108: a row address buffer configured to store the row address among the received addresses; a column address buffer configured to store the column address among the received addresses; that is at least one of 106 and 108 stores a range of address operable to refresh related cells).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights