DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 12/10/2024.
Claims 1-23 are pending. Claims 1, 10, 15 and 19 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
F) Under MPEP 711.01 and 37 CFR 1.138, a patent applicant can expressly abandon a parent application in favor of a Continuation-in-Part (CIP) or Continuity (CON) application to ensure priority date.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Information Disclosure Statement
4. No IDS has been filed as of this office action date.
No Priority
5. No priority claimed. See ADS.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Drawings
6. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include reference character(s) associated with Figure 7-Figure 13 (and overall Figures 7-13) not mentioned in the spec description.
Corrected drawing sheets in compliance with 37 CFR 1.121 (d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121 (b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121 (d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Spec Objections
7. Specification is objected to under 37CFR 1.74 (see MPEP 608.01(f) and 608.01(g)). 37 C.F.R. 1.74 teaches that reference to drawings must be present: “…When there are drawings, there shall be a brief description of the several views of the drawings and the detailed description of the invention shall refer to the different views by specifying the numbers of the figures, and to the different parts by use of reference letters or numerals…”. There is no description or reference to drawings Figure 7-Figure 13. See e.g., para [0010] and para [0074] both of which marks the last figures being described. The specification must contain or be amended to contain proper reference to the existence of drawings. Correction is required. No new matter should be introduced.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-10, and 13-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FUJIWARA et al. (US 2023/0290428 A1).
Regarding independent claim 1, FUJIWARA teaches an apparatus (Fig. 1: 100 semiconductor device; para [0014]) comprising:
a bank of a memory array (Fig. 1 and para [0015]: Banks) having a column plane (para [0013]: “second column plane”. See Fig. 2: CP1) including a first column select signal (Fig. 2: CS1 “column select signal”) and a second column select signal (Fig. 2: CS33 “column select signal”); and
a plurality of fuses (Fig. 1: 125 fuse array) configured to store a corresponding plurality of swap bits (para [0017]: address and associated information stored in fuse to implement function “…address should be swapped…”. See also para [0043]: bits used for swapping),
wherein the plurality of swap bits are configured to be set to map the first column select signal (Fig. 2: CS1) to an address of the second column select (Fig. 2: CS33) signal (“…swapping the first address in the second column plane with a second address in the second column plane such that the second set of bit lines is associated with the second address…”. See Fig. 6: 620 in context of para [0034], para [0070], para [0013]).
Regarding claim 2, FUJIWARA teaches the apparatus of claim 1, wherein a number of the plurality of swap bits is two (para [0043]: “…swap logic…may store…binary value 11 in…latch 314 for one of the column planes…which may cause… signal CSB to be activated…instead of CSA…”).
Regarding claim 3, FUJIWARA teaches the apparatus of claim 1, wherein the plurality of swap bits are configured to flip a corresponding number of most significant bits of the address when set (para [0013]: “…CS value may be remapped by swapping a logical level of one or more bits …such as a most significant bit…of the column address associated with that CS value…”. See also para [0043])
Regarding claim 4, FUJIWARA teaches the apparatus of claim 1, further comprising a fuse array including the plurality of fuses (para [0017]: “fuse array”).
Regarding claim 5, FUJIWARA teaches the apparatus of claim 4, further comprising a fuse register (Fig. 3: FzSwap which is in Fig. 1: 126) configured to receive and store the plurality of swap bits (para [0041]) from the fuse array (see Fig. 1: 125 in relation to Fig. 3).
Regarding claim 6, FUJIWARA teaches the apparatus of claim 1, further comprising a fuse bank including the plurality of fuses (para [0017]: e.g. fuse array with unprogrammed fuses).
Regarding claim 7, FUJIWARA teaches the apparatus of claim 1, wherein the bank further comprises a global column redundancy (GCR) plane (Fig. 2: 230) comprising a plurality of column select signals (Fig. 2 in context of para [0032]), and
the apparatus further comprises a second plurality of fuses configured to be set to map the second column select signal to a column select of the plurality of column select signals of the GCR plane (Fig. 2: CS1 in CP0 can be mapped to RCS1 in GCR-CP. See para [0034]).
Regarding claim 8, FUJIWARA teaches the apparatus of claim 1, wherein the bank is configured to be arranged in one of a plurality of storage modes (for example data write mode with redundancy and without redundancy; see e.g. in context of para [0012]).
Regarding claim 9, FUJIWARA teaches the apparatus of claim 8, wherein each of the plurality of storage modes stores a different amount of metadata (Redundancy mode write requires repair related metadata. Bypassing redundancy mode does not require repair related metadata).
Regarding independent claim 10, FUJIWARA teaches a system (System of Fig. 1. See Fig. 1-Fig. 6 for illustrated components and functionality) comprising:
a memory device (Fig. 1: 100 semiconductor device) including:
a memory array (para [0015], Fig. 1: 118 memory array) having a physical column plane (para [0013]: “second column plane”. See Fig. 2: CP1) including a first column select signal (Fig. 2: CS1 “column select signal”) and a second column select signal (Fig. 2: CS33 “column select signal”); and
a plurality of fuses (Fig. 1: 125 fuse array) configured to store a corresponding plurality of swap bits (para [0017]: address and associated information stored in fuse to implement function “…address should be swapped…”. See also para [0043]: bits used for swapping),
wherein the plurality of swap bits are configured to be set to map the first column select signal (Fig. 2: CS1) to an address of the second column select signal (Fig. 2: CS33. See “…swapping the first address in the second column plane with a second address in the second column plane such that the second set of bit lines is associated with the second address…”. See Fig. 6: 620 in context of para [0034], para [0070], para [0013]); and
a controller (memory controller, Fig. 3: 300 GCR logic, swap logic combined) coupled to the memory device (Fig. 1: 100),
the controller configured to provide at least one command (Fig. 3: CA, CA’) to set one or more of the plurality of swap bits (para [0037]: “…GCR logic … several components…GCR operations and swapping addresses of selected CS sets within a column plane…”)
Regarding claim 13, FUJIWARA teaches the system of claim 10, wherein the one or more of plurality of swap bits are configured to flip a corresponding number of most significant bits of the address when set. (See claim 3 rejection analysis. See para [0043], para [0057])
Regarding claim 14, FUJIWARA teaches the system of claim 13, wherein the number of most significant bits is two. (See claim 2-3 rejection analysis)
Regarding independent claim 15, FUJIWARA teaches a method, comprising:
receiving, at a memory device, a command indicating one or more of a plurality of swap bits to set;
responsive to the command, programming one or more of a plurality of fuses to set the one or more of the plurality of swap bits; and
responsive to programming the one or more of the plurality of fuses, remapping an address from a first column select of a column plane to a second column select of the column plane. (claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 16, FUJIWARA teaches the method of claim 15, wherein the programming comprises setting two of the plurality of fuses to flip two bits of the address. (claim is drafted as in method format, substantially identical to the functionality recited in claims 2-3, and is therefore rejected for the same reasons as claim 2-3).
Regarding claim 17, FUJIWARA teaches the method of claim 16, wherein the two bits comprise two most significant bits of the address. (claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3).
Regarding claim 18, FUJIWARA teaches the method of claim 15, further comprising broadcasting the plurality of swap bits from the plurality of fuses to a fuse register. (claim is drafted as in method format, substantially identical to the functionality recited in claim 5, and is therefore rejected for the same reasons as claim 5).
Regarding independent claim 19, FUJIWARA teaches a method, comprising: providing to a memory device, a command indicating one or more of a plurality of swap bits to set by programming one or more fuses of the memory device to cause the memory device to remap an address from a first column select of a column plane to a second column select of the column plane of a memory array of the memory device. (claim is drafted as in method format, substantially identical to the functionality recited in claim 10, and is therefore rejected for the same reasons as claim 10).
Regarding claim 20, FUJIWARA teaches the method of claim 19, further comprising: testing the memory device (para [0020], para [0069]); and
responsive to the testing, determining the first column select is defective, wherein the command is provided responsive to the determining (para [0020] is inclusive of the limitation).
Regarding claim 21, FUJIWARA teaches the method of claim 19, further comprising packaging the memory device (limitation is not treated since claim language very broadly claims method of packaging memory device which is applicable for all memory device).
Regarding claim 22, FUJIWARA teaches the method of claim 19, wherein the command is provided by a memory controller (memory controller, Fig. 3: 300 GCR logic, swap logic combined).
Regarding claim 23, FUJIWARA teaches the method of claim 19, wherein the command is provided by a testing device (para [0020], para [0069]: “repair analyzer” or tester is used).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Johnson et al. (US 2022/0005541 A1): Fig. 1-Fig. 7 disclosure applicable for all claims. He et al. (US 2022/0319581 A1): Fig. 1-Fig. 8 disclosure applicable for all claims. Amrie Bin Shaari et al. (US 2021/0241842 A1): Fig. 1-Fig. 9 disclosure applicable for all claims. Ferris et al. (US 5163023 A): Ferris teaches a memory device (Fig. 1 “memory circuit”, see Fig. 1-Fig. 5 for illustrated components and functionality) comprising: a first column plane (Fig. 4: Group 6) comprising: a first edge (Fig. 4: left edge of Group 6); a second edge opposite the first edge (Fig. 4: right edge of Group 6); and a first number of digit lines (col. 4, lines 18-26: “…groups of columns BIT 0 to BIT 7…”) arranged between the first edge and the second edge (see Fig. 4: Group 6 arrangement), the first number of digit lines configured to access a number of memory cells of the first column plane (in context of col. 4, lines 18-26: bit lines, data lines associated with BIT 0-BIT 7 in Group 6); a second column plane (Fig. 4: Group 7, 14 combined) positioned adjacent to the first column plane (see Fig. 4 Group arrangements), the second column plane comprising: a third edge (Fig. 4: left edge of Group 7) positioned adjacent to the second edge of the first column plane (see Fig. 4); a fourth edge (Fig. 4: 14) opposite the third edge (see Fig. 4); and a second number of digit lines (in context of col. 4, lines 18-26: bit lines, data lines associated with BIT 0 to SPARE BIT) arranged between the third edge and the fourth edge (see Fig. 4 arrangement) ; and a data-steering circuit (col. 2, line 27: “routing circuitry”, see Fig. 4) configured to logically relate (col. 2, lines 27-56: connect with condition of fault establishment) a first digit line (column associated with BIT 0 bit line in Group 6) of the first number of digit lines to a second digit line (column associated with SPARE BIT bitline in Group 7, 14) of the second number of digit lines (col. 2, lines 27-56: spare column can be connected to most significant bit or least significant bit within group), the first digit line (column associated with BIT 0 bit line in Group 6) proximate to the first edge (Fig. 4: left edge of Group 6), the second digit line (column associated with SPARE BIT bitline in Group 7, 14) proximate to the fourth edge (Fig. 4: 14).
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further any objections associated with the application must be over-come.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
Prosecution Insights