DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicant’s amendment submitted on June 19, 2026. In virtue of this amendment, claims 1-20 are now pending in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/08/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyaguchi et al. (US 2007/0273456 of record).
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With respect to claim 1, Miyaguchi discloses in figures 27-28 an apparatus as a first phase delay unit element (681-68n, e.g., phase delay units or phase shifters thereof) of a phase shifter (figure 28 shows a phase shifter) configured for a beamforming system (see figure 27), the apparatus comprising: a first path switch (103, e.g., a first path switch) configured to control an activation and a deactivation of a first path (Path1, e.g., a first path being ON or OFF by the first path switch 103); a first path resonator (108, e.g., a capacitor formed as a resonator thereof) connected in parallel across both ends of the first path switch (see figure 28), and having an impedance capable of realizing a parallel resonance with an impedance seen at both ends of the first path switch (figure 28 shows a parallel connection feature between the switch 103 and the capacitor 108 thereof) when the first path switch is in a control mode for the deactivation of the first path (see figure 28); a first inductor (105, e.g., a first inductor) positioned on a second path (Path2, e.g., a second path) and connected to an input terminal (Tin) or an output terminal (Tout) of a phase delay unit element (see figure 28), the first inductor being configured to render an impedance seen from a connected terminal (Tc) to exhibit an inductive characteristic (see figure 28); a second inductor (106, e.g., a second inductor) positioned on the second path and connected to another input terminal (101) or another output terminal (102) of the phase delay unit element (see figure 28), the second inductor being configured to render an impedance seen from a connected terminal (Tc) to exhibit an inductive characteristic (see figure 28); and a path-based impedance converter (104, 107, e.g., formed as an impedance converter thereof) positioned on the second path, the path-based impedance converter being configured to convert (see figure 28), according to an external control signal (having a control signal by a gate of the switch 103 thereof) for selecting the first path or the second path (see figure 28), an impedance (having an impedance combining the first and second inductors thereof) thereof into an impedance generating a phase delay (having an phase shifting on the second path) on the second path including the first inductor and the second inductor or into an impedance such that an impedance as large as possible is seen at both terminals (Tin-Tout or 101-102) of the second path including the first inductor and the second inductor (see figure 28).
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With respect to claim 2, Miyaguchi discloses that wherein the first path switch is configured to be controlled such that the first path switch is turned on so that a signal is transmitted to the first path (figure 28 shows that when the switch 103 turned on or closed, a signal is transmitted to the Path1).
With respect to claim 3, Miyaguchi discloses that wherein the first path switch is configured to be controlled such that the first path switch is turned off so that a signal is transmitted to the second path, so that the signal passes through the second path via the first inductor and the second inductor (figure 28 shows that when the switch 103 turned off or opened, a signal is transmitted to the Path2).
With respect to claim 4, Miyaguchi discloses that wherein the path-based impedance converter has an impedance that realizes a specific phase delay (having a phase shifting delay of the phase shifter 681 thereof) on the second path in the frequency band of the signal that is transmitted, the second path including the first inductor and the second inductor (see figure 28 and paragraph 0002).
With respect to claim 5, Miyaguchi discloses that wherein, in order to minimize a signal leakage from the both terminals of the second path to the first path switch, the first path resonator has an impedance capable of realizing a parallel resonance of an impedance of the first path switch which is connected in parallel with the first path resonator and which is turned off (figure 28 shows a parallel resonance feature between the resonator 108 and the first switch 103).
With respect to claim 6, Miyaguchi discloses that a second phase delay unit element (382, e.g., a second phase shifter or phase delay unit) and a third phase delay unit element (68n, e.g., a third phase shifter or phase delay unit) have the same structure as the first phase delay unit element but have different parameter values, and the phase shifter is formed by combining the first phase delay unit element, the second phase delay unit element, and the third phase delay unit element (see figure 27).
With respect to claim 7, Miyaguchi discloses that wherein the first path switch comprises at least one of an NMOS or a PMOS of a complementary metal-oxide-semiconductor (CMOS) semiconductor process (paragraph 0002, e.g., FET 103 and FET 104).
With respect to claim 8, Miyaguchi discloses that wherein the first path resonator is configured as an inductor (figure 11 shows the first path resonator including a capacitor 28 and an inductor 15).
With respect to claim 9, Miyaguchi discloses that wherein the path-based impedance converter utilizes a varactor (19, 3b’, e.g., a varactor) in which a capacitance (19, e.g., a capacitor) thereof is changed by the external control signal (see figure 11).
With respect to claim 10, Miyaguchi discloses that wherein the path-based impedance converter comprises a path-based control switch (3b’, e.g., a switch) and a delay capacitor (19, e.g., a capacitor) that is connected in series with the path-based control switch (see figure 11).
With respect to claim 11, Miyaguchi discloses that wherein the delay capacitor has a capacitance value that causes a specific phase delay by being in conjunction with the first inductor and the second inductor (see figure 11).
With respect to claim 14, Miyaguchi discloses that wherein the first path resonator is not an element through which a signal passes, and is configured to minimize a signal leakage toward the first path while a signal passes through the second path (figure 28 shows that when Path1 is off and the Path2 is on, the capacitor 108 or the resonator 108 to reduce the leakage signal toward the Path1 thereof).
With respect to claim 15, Miyaguchi discloses that wherein the first path resonator is configured by sharing a ground layer (109, e.g., GND) between the first inductor and the second inductor (see figure 28).
With respect to claim 16, Miyaguchi discloses that wherein the first path resonator is configured in a form in which a plurality of metal layers is connected in parallel to each other with vias (figures 12-15 shows a plurality of metal layers being connected in parallel via connecting lines thereof).
With respect to claim 17, Miyaguchi discloses in figures 27-28 an operation method of a first phase delay unit element (681, e.g., a phase delay unit or a phase shifter thereof) of a phase shifter (figure 28 shows a phase shifter) configured for a beamforming system (see figure 27), the operation method comprising: controlling, by a first path switch (103, e.g., a first path switch), an activation and a deactivation of a first path (Path1, e.g., a first path being ON or OFF by the first path switch 103); performing, by a first path resonator (108, e.g., a capacitor formed as a resonator thereof) connected in parallel across both ends of the first path switch (see figure 28), a parallel resonance of an impedance seen at both ends of the first path switch (figure 28 shows a parallel connection feature between the switch 103 and the capacitor 108 thereof) when the first path switch is in a control mode (at the gate terminal of the switch 103) for the deactivation of the first path (see figure 28); operating a first inductor (105, e.g., a first inductor) such that the first inductor positioned on a second path (Path2, e.g., a second path) and connected to an input terminal (Tin) or an output terminal (Tout) of a phase delay unit element (see figure 28, e.g., a phase shifter) renders an impedance seen from a connected terminal (Tc) to exhibit an inductive characteristic (see figure 28); operating a second inductor (106, e.g., a second inductor) such that the second inductor positioned on the second path and connected to another input terminal (101) or another output terminal (102) of the phase delay unit element renders an impedance seen from a connected terminal (Tc) to exhibit an inductive characteristic (see figure 28); and operating a path-based impedance converter (104, 107, e.g., formed as an impedance converter thereof) such that the path-based impedance converter to convert (see figure 28), according to an external control signal (having a control signal by a gate of the switch 103 thereof) for selecting the first path or the second path (see figure 28), an impedance (having an impedance combining the first and second inductors thereof) thereof into an impedance generating a phase delay (having an phase shifting on the second path) on the second path including the first inductor and the second inductor or into an impedance such that an impedance as large as possible is seen at both terminals (Tin-Tout or 101-102) of the second path including the first inductor and the second inductor (see figure 28).
With respect to claim 18, Miyaguchi discloses that wherein the first path switch is configured to be controlled such that the first path switch is turned on so that a signal is transmitted to the first path (figure 28 shows that when the switch 103 turned on or closed, a signal is transmitted to the Path1).
With respect to claim 19, Miyaguchi discloses that wherein the first path switch is configured to be controlled such that the first path switch is turned off so that a signal is transmitted to the second path, so that the signal passes through the second path via the first inductor and the second inductor (figure 28 shows that when the switch 103 turned off or opened, a signal is transmitted to the Path2).
With respect to claim 20, Miyaguchi discloses that wherein the path-based impedance converter has an impedance that realizes a specific phase delay (having a phase shifting delay of the phase shifter 681 thereof) on the second path in the frequency band of the signal that is transmitted, the second path including the first inductor and the second inductor (see figure 28 and paragraph 0002).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Miyaguchi et al. (US 2007/0273456) in view of Shrivastava et al. (US 12,101,072).
With respect to claim 12, Miyaguchi discloses all claimed limitations, as expressly recited in claim 1, except for specifying that wherein the first path switch comprises a combination of a plurality of sub-switches.
Shrivastava discloses in figure 3A a phase shifter comprising a first path switch (S11-S13, e.g., a first path switch in a first path P1) and a second path switch (S21-S23, e.g., a second path switch in a second path P2), wherein the first path switch comprises a combination of a plurality of sub-switches (figure 3A shows the first patch switch having two switches S11 and S13).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the apparatus of Miyaguchi with a plurality of switches in a first path as taught by Shrivastava for the purpose of resulting in a substantial decrease in the glitch at the output terminal thereof since this configuration for the stated purpose would have been obvious as evidenced by the teaching of Shrivastava (column 5 in lines 45-50).
With respect to claim 13, the combination of Miyaguchi and Shrivastava disclose that wherein an insertion loss of the plurality of sub-switches is determined on the basis of an insertion loss corresponding to the second path (see figure 3A and column 5 in lines 40-52 of Shrivastava).
Response to Arguments
Applicant's arguments filed 06/19/2026 have been fully considered but they are not persuasive.
Applicant argued that “the technical features of the claimed first path resonator and path-based impedance converter are not disclosed in Miyaguchi”.
However, Examiner disagrees as few following reasons below:
A: Here is the phase delay circuit of the instant application in figure 4 having a first path resonator 212 and a path-based impedance converter 215 thereof.
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B: Figure 28 of Miyaguchi shows the phase delay circuit having a resonator 108 and a path-based impedance converter 104-107 thereof.
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C: Here is defined a resonant circuit as below:
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Thus, any L, C, LC or RLC circuits are defined as a resonant circuit thereof. Therefore, the capacitor 108 could perform a function as a resonant circuit as claimed and figure 11 also shows a LC resonant circuit thereof.
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D: Figures 11 and 28 of Miyaguchi also shows a path-based impedance converter structure similar as the converter 215 in figure 4 of the instant application.
E: However, claim 1 is not described the functions of the first path resonator and the path-based impedance converter being different with the resonator and the converter of Miyaguchi. Thus, any differences there-between in structures or function would need to describe in the claim thereof.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Shin et al. – US 2011/0199141
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUNG X LE/Primary Examiner, Art Unit 2845 August 25, 2026
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