DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takai et al. (US Pub. 2006/0274586).
Regarding claim 1, Fig. 4 of Takai discloses an apparatus comprising: a memory array [11] configured to be arranged based on one of a plurality of storage modes, wherein the memory array comprises a plurality of column selects [by column control 14] and a plurality of redundant column selects [column control 14 for redundant column 12];
a fuse array [20] comprising a plurality of fuses [Fuse & fuse latch 21], wherein the plurality of fuses are configured to be programmed to store address information for a portion of the plurality of column [paragraph 0083] selects remapped to the plurality of redundant column selects for the plurality of storage modes [as discloses in paragraphs 0082 to 0084, when a defected column in array 11 is detected, the address of the defected column is mapped to the a redundancy column]; and
a plurality of fuse registers [16] configured to receive and store the address information from the fuse array [paragraph 0086].
Regarding claims 2 and 14, Fig. 34 of Takai discloses wherein the plurality of fuses [21, Fig. 4] is further configured to store address shift information [defected address, paragraph 0081], wherein the address shift information indicates an amount to shift an address included in the address information based on a storage mode of the plurality of storage modes [as shows in Fig. 34, address mapping, including map shift (from one location to another location)], wherein the plurality of fuse registers [16, Fig. 4] are further configured to receive and store the address shift information [the transfer FuseData in Fig. 34].
Regarding claim 7, Fig. 1 of Takai discloses wherein each fuse of the plurality of fuses stores one bit.
Regarding claim 11, Fig. 4 of Takai discloses further comprising a fuse logic circuit [22] configured to provide the address information from the fuse array [21] to the fuse registers [16].
Regarding claim 12, Fig. 4 of Takai discloses wherein the memory array comprises a plurality of banks, wherein individual ones of the plurality of banks are associated with different portions of the plurality of fuse registers [paragraph 0185]
Regarding claim 13, Fig. 4 of Takai discloses method, comprising:
receiving a command and address information at a memory device from an external device [since the memory device is being operated by a user, it is inherent that the command and address are received from an external device [user];
programming a plurality of fuses [21] of a fuse array [20] of the memory device with the address information based on the command, wherein the address information indicates a plurality of column selects [paragraph 0083] remapped to a plurality of redundant column selects for a plurality of storage modes of the memory device [as discloses in paragraphs 0082 to 0084, when a defected column in array 11 is detected, the address of the defected column is mapped to the a redundancy column]; and
broadcasting [sending] the address information from the fuse array [20] to a plurality of fuse registers [16, paragraph 0086].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is are rejected under 35 U.S.C. 103 as being unpatentable over Takai et al. (US Pub. 2006/0274586).
Regarding claim 6, Fig. 32 and paragraphs 0088 and 0090 discloses fuses stores more than 10 bits. But does not specifically disclose twelve bits for address and four bits for shift information. However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to designated 12 bits for address and 4 bits for shift information, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 3-5, 8-10, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3-5, the prior art does not teach or suggest either alone or in combination an address shifter circuit configured to receive the address information and the address shift information from the fuse registers, wherein the address shifter circuit is configured to provide the address when disabled by an enable signal and provide a shifted address based on the address shift information and the address when enabled by the enable signal.
Regarding claims 8-10, the prior art does not teach or suggest either alone or in combination a shift logic circuit configured to output a shift control signal indicating address shift information, wherein the address shift information indicates an amount to shift an address included in the address information based on a storage mode of the plurality of storage modes, when enabled by an enable signal; and an address shifter circuit configured to receive the address information from the plurality of fuse registers and the address shift information from the shift logic circuit and output the address or a shifted address based on the shift control signal.
Regarding claims 15-16, the prior art does not teach or suggest either alone or in combination receiving a mode register write command and a value indicating a storage mode of the plurality of storage modes; writing the value to a mode register; when the storage mode is a default storage mode of the plurality of storage modes, providing an inactive enable signal to disable an address shifter circuit; and when the storage mode is the non-default storage mode, providing an active enable signal to enable the address shifter circuit.
Regarding claims 17-20, the prior art does not teach or suggest either alone or in combination providing the address information to an address shifter circuit and a shift logic circuit; determining, with the shift logic circuit an amount to shift an address of the address information when the memory device is in a non-default storage mode of the plurality of storage modes; and providing a shift control signal from the shift logic circuit to the address shifter circuit indicating the amount.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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