DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 18/976,631 on February 6, 2026. Claims 1-20 are pending. Please note Claims 8-15 have been withdrawn in light of an earlier restriction requirement.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 26, 2026 has been entered.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1, 2 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over In et al. ( US 2021/0166635 A1 ) in view of Kang ( US 2019/0103060 A1 ).
In teaches in Claim 1:
A display device ( Figure 1, [0042] discloses an organic light-emitting display device 100 ) comprising:
a pixel unit ( Figure 1, [0043] discloses a display panel 110 has a plurality of pixels 111 ) including first pixel rows connected to first emission lines and second pixel rows connected to second emission lines, wherein the second pixel rows alternate with the first pixel rows ( Figure 6, [0071] discloses each pixel row is connected to an emission line, namely EL(1), EL(2), etc. Please note EL(1), EL(3), and in general, odd rows, as being associated with first pixel rows and EL(2), EL(4), and in general, even rows, as being associated with second pixel rows );
an emission driver including first emission stages connected to the first emission lines and second emission stages connected to the second emission lines ( Figure 1, [0072] discloses an emission driver 150-1 which provides emission signals EM(1) to EM(k). Please note these emission signals along the emission lines shown in Figure 6. As for the first emission stages, please note the odd-numbered emission drivers 150-11 and for the second emission stages, please note the even-numbered drivers 150-12 ); and
a scan driver including first scan stages connected to the first pixel rows and second scan stages connected to the second pixel rows ( Figure 8, [0081] discloses a scan driver 135-1 which can be connected to scan lines SL(1), SL(2), etc. As is the case with the above, please note the odd-numbered and even-numbered scan lines associated with the first pixel rows and second pixel rows, respectively ),
wherein one of the first emission stages is connected to a first emission start line, one of the second emission stages is connected to a second emission start line ( Figure 6, [0054] discloses for the first/odd-numbered emission drivers 150-11, please note the emission start signal ESP to the first emission stage. Likewise, for the second/even-numbered emission drivers 150-12, please note a different emission start signal ESP as well ),
each of the first emission stages, except the first emission stage connected to the first emission start line, is connected to a first emission line of a previous first emission stage ( Figure 6. [0054] discloses EST(3) is connected to an output of EST(1), namely EM(1)/EL(1) ) and
each of the second emission stages, except the second emission stage connected to the second emission start line, is connected to a second emission line of a previous second emission stage, ( Figure 6, [0054] discloses EST(4) is connected to an output of EST(2), namely EM(2)/EL(2) )
the first emission stage is configured to receive a first emission control signal via the first emission start line, the first emission control signal defines non-emission periods and emission periods of the first pixel rows during a frame period ( Figure 6, [0054], [0021] discloses the odd-numbered emission driver 150-11 with a first stage EST(1) receiving an ESP signal along the shown start line, as well as ECLKS(1) (read as a first emission control signal). [0073] notes ECLKS(1) is applied based on ESP (read as via). Figure 3, [0054] shows SF1 for the odd-numbered emission stages, including emission and non-emission periods being defined by the low and high states. To clarify, [0045] discloses one frame 1F (read as the claimed frame period) which comprises SF1 and SF2 ),
the second emission stage is configured to receive a second emission control signal via the second emission start line, the second emission control signal defines non-emission periods and emission periods of the second pixel rows during the frame period ( Figure 6, [0054], [0021] discloses the even-numbered emission driver 150-11 with a first stage EST(2) receiving an ESP signal along the shown start line, as well as ECLKS(2) (read as a second emission control signal). [0073] notes ECLKS(2) is applied based on ESP (read as via). To clarify, EST(2) receives a second/separate ESP wiring as well. Figure 4, [0054] shows SF2 for the even-numbered emission stages, including emission and non-emission periods being defined by the low and high states. To clarify again, [0045] discloses one frame 1F (read as the claimed frame period) which comprises SF1 and SF2 ), and
pixels in at least one of the first pixel rows and the second pixel rows are configured to emit light at any point in time during the frame period ( Figures 3 and 4 show during SF1 and SF2 which make up 1F and pixels emit light, in conjunction with the emission drivers, during at least one of SF1 and SF2 ); but
In may not explicitly teach “a turn-off level of the first emission control signal and a turn-off level of the second emission control signal never overlap temporally during the frame period.”
In does teach: Figure 3 and 4 show the periods for SF1 and SF2, which correspond to the odd and even-numbered emission drivers. Please note the distinct periods, i.e. lack of overlap.
To emphasize on this, multiple emission control signals, Kang teaches of a pixel circuit with multiple OLED elements, ( Kang, Figure 10, [0113] ). Notably, each OLED element is controlled by a different emission control signal, with OLED1 being controlled by EMT and OLED2 being controlled by EMB. This is similar in sense to In who teaches of multiple OLEDs being controlled by different emission control signals. Furthermore, Kang teaches in Figure 11, [0115] of the on/off periods for EMB and EMT and it is seen the turn-off levels of these (as evidenced by the ON/OFF denotations for the associated OLEDs) never overlap temporally during the frame period. To clarify, when one OLED is emitting, the other is not and this lack of overlap is evident. As combined with In, who already teaches of alternate driving of emission drivers in Figures 3 and 4 (alternate meaning non-overlap here), an explicit turn-off level for the emission signals is taught.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date o the invention, to implement the alternating of emission signals, as taught by Kang, with the motivation that only one OLED would emit at a time, preventing left-right reversal, ( Kang, [0082] ).
In teaches in Claim 2:
The display device according to claim 1, wherein the first emission stage is configured to receive another turn on level of the first emission control signal after the second emission stage has received a turn on level of the second emission control signal. ( Figure 6, [0073]-[0074] discloses after ESP is applied to EST(1) and EST(2), first emission clock signals ECLKS(1) and second emission clock signals ECLKS(2) are applied to (thus, turn-on levels) the subsequent stages in each of 150-11 and 150-12. The odd and even stages correspond to SF1 and SF2, respectively, as shown in Figures 3 and 4. Respectfully, it is clear this repeats during the next frame 1F in which case the odd-numbered emission driver will receive another turn on level of ESP )
In teaches in Claim 16:
A display device ( Figure 1, [0042] discloses an organic light-emitting display device 100 ) comprising:
a pixel unit ( Figure 1, [0043] discloses a display panel 110 has a plurality of pixels 111 ) including first pixel rows connected to first emission lines and second pixel rows connected to second emission lines, wherein the second pixel rows alternate with the first pixel rows ( Figure 6, [0071] discloses each pixel row is connected to an emission line, namely EL(1), EL(2), etc. Please note EL(1), EL(3), and in general, odd rows, as being associated with first pixel rows and EL(2), EL(4), and in general, even rows, as being associated with second pixel rows );
an emission driver including first emission stages connected to the first emission lines and second emission stages connected to the second emission lines ( Figure 1, [0072] discloses an emission driver 150-1 which provides emission signals EM(1) to EM(k). Please note these emission signals along the emission lines shown in Figure 6. As for the first emission stages, please note the odd-numbered emission drivers 150-11 and for the second emission stages, please note the even-numbered drivers 150-12 ); and
a scan driver including first scan stages connected to the first pixel rows and second scan stages connected to the second pixel rows ( Figure 8, [0081] discloses a scan driver 135-1 which can be connected to scan lines SL(1), SL(2), etc. As is the case with the above, please note the odd-numbered and even-numbered scan lines associated with the first pixel rows and second pixel rows, respectively ),
wherein one of the first emission stages is connected to a first emission start line ( Figure 6, [0054] discloses for the first/odd-numbered emission drivers 150-11, please note the emission start signal ESP to the first emission stage ), and
wherein each of the first emission stages, except the first emission stage connected to the first emission start line, is connected to a first emission line of a previous first emission stage, ( Figure 6. [0054] discloses EST(3) is connected to an output of EST(1), namely EM(1)/EL(1) )
each of the first emission stages, except the first emission stage connected to the first emission start line, is connected to a first emission line of a previous first emission stage, one of the second emission stages is connected to a second emission start line to receive a second emission control signal ( Figure 6, [0054] discloses for the first/odd-numbered emission drivers 150-11, please note the emission start signal ESP to the first emission stage. Likewise, for the second/even-numbered emission drivers 150-12, please note a different emission start signal ESP as well. As such, these rows are controlled by the respective ESP signals input to each of these drivers and these are controlled by ECLKS(1) (for the odd) and ECLKS(2) for the even (read as a first emission control signal and second emission control signal, respectively) ),
each of the second emission stages, except the second emission stage connected to the second emission start line, is connected to a second emission line of a previous second emission stage ( Figure 6. [0054] discloses EST(4) is connected to an output of EST(2), namely EM(2)/EL(2) ),
the first pixel rows are controlled by the first emission control signal, the second pixel rows are controlled by the second emission control signal ( Figure 6, [0071] and as noted above, the interpreted first pixel row corresponds to the odd-numbered emission driver and the interpreted second pixel row corresponds to the even-numbered emission driver. Please note the above with regards to the ECKLS(1) for the odd and ECKLS(2) for the even ), and
at any point in time in a frame period, at least one of the first emission control signal and the second emission control signal has a turn on level ( Figure 6, [0054], [0021] discloses the odd-numbered emission driver 150-11 with a first stage EST(1) receiving an ESP signal along the shown start line, as well as ECLKS(1) (read as a first emission control signal). [0073] notes ECLKS(1) is applied based on ESP (read as via). Figure 3, [0054] shows SF1 for the odd-numbered emission stages, including emission and non-emission periods being defined by the low and high states. Figure 4, [0054] shows SF2 for the even-numbered emission stages, including emission and non-emission periods being defined by the low and high states. To clarify, [0045] discloses one frame 1F (read as the claimed frame period) which comprises SF1 and SF2. Furthermore, Figures 3 and 4 show during SF1 and SF2 which make up 1F and pixels emit light, in conjunction with the emission drivers, during at least one of SF1 and SF2 ); but
In may not explicitly teach “a turn-off level of the first emission control signal and a turn-off level of the second emission control signal never overlap temporally during the frame period.”
In does teach: Figure 3 and 4 show the periods for SF1 and SF2, which correspond to the odd and even-numbered emission drivers. Please note the distinct periods, i.e. lack of overlap.
To emphasize on this, multiple emission control signals, Kang teaches of a pixel circuit with multiple OLED elements, ( Kang, Figure 10, [0113] ). Notably, each OLED element is controlled by a different emission control signal, with OLED1 being controlled by EMT and OLED2 being controlled by EMB. This is similar in sense to In who teaches of multiple OLEDs being controlled by different emission control signals. Furthermore, Kang teaches in Figure 11, [0115] of the on/off periods for EMB and EMT and it is seen the turn-off levels of these (as evidenced by the ON/OFF denotations for the associated OLEDs) never overlap temporally during the frame period. To clarify, when one OLED is emitting, the other is not and this lack of overlap is evident. As combined with In, who already teaches of alternate driving of emission drivers in Figures 3 and 4 (alternate meaning non-overlap here), an explicit turn-off level for the emission signals is taught.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date o the invention, to implement the alternating of emission signals, as taught by Kang, with the motivation that only one OLED would emit at a time, preventing left-right reversal, ( Kang, [0082] ).
In teaches in Claim 17:
The display device of claim 16, wherein during a frame period, the first emission control signal defines non-emission periods corresponding to a turn-off level of pixels in the first pixel rows and emission periods corresponding to turn-on level of pixels in the second pixel rows ( As noted above, ESP, as shown in Figures 3 and 4, [0054] disclose ESP for the odd and even-numbered emission drivers are applied during SF1 and SF2, respectively. Respectfully, this is a turn-on and turn-off levels ),
during a frame period, each of the first emission control signal and the second emission control signal includes two emission cycles, each of the emission cycles corresponding to a successive non-emission period and an emission period. ( Figures 3 and 4 disclose SF1 and SF2, i.e. two emission cycles and for each of the odd and even-numbered emission drivers, there is a successive non-emission and emission period )
In and Kang teach in Claim 18:
The display device of claim 1, wherein the non-emission periods of the first pixel rows and the non-emission periods of the second pixel rows do not overlap during the frame period. ( Figure 3 and 4 show the periods for SF1 and SF2, which correspond to the odd and even-numbered emission drivers. Please note the distinct periods, i.e. lack of overlap. Furthermore, as combined with Kang, Figure 11 shows the non-emission periods for the OLEDs, noted as ON and OFF, do not overlap )
In teaches in Claim 19:
The display device of claim 19, wherein at any point in time in the frame period, at least one of the pixels in the first pixel rows and pixels in the second pixel rods are turned on. ( Figures 3 and 4 show during SF1 and SF2 which make up 1F and pixels emit light, in conjunction with the emission drivers, during at least one of SF1 and SF2 )
In teaches in Claim 20:
An electronic device ( Abstract details a device ) comprising:
a display device ( Figure 1, [0042] discloses an organic light-emitting display device 100 ); and
a processor configured to control the display device ( Figure 11, [0093] discloses a processor ), the display device comprising:
a pixel unit ( Figure 1, [0043] discloses a display panel 110 has a plurality of pixels 111 ) including first pixel rows connected to first emission lines and second pixel rows connected to second emission lines, wherein the second pixel rows alternate with the first
pixel rows ( Figure 6, [0071] discloses each pixel row is connected to an emission line, namely EL(1), EL(2), etc. Please note EL(1), EL(3), and in general, odd rows, as being associated with first pixel rows and EL(2), EL(4), and in general, even rows, as being associated with second pixel rows );
an emission driver including first emission stages connected to the first emission lines
and second emission stages connected to the second emission lines ( Figure 1, [0072] discloses an emission driver 150-1 which provides emission signals EM(1) to EM(k). Please note these emission signals along the emission lines shown in Figure 6. As for the first emission stages, please note the odd-numbered emission drivers 150-11 and for the second emission stages, please note the even-numbered drivers 150-12 ); and
a scan driver including first scan stages connected to the first pixel rows and second scan
stages connected to the second pixel rows ( Figure 8, [0081] discloses a scan driver 135-1 which can be connected to scan lines SL(1), SL(2), etc. As is the case with the above, please note the odd-numbered and even-numbered scan lines associated with the first pixel rows and second pixel rows, respectively ), wherein
one of the first emission stages is connected to a first emission start line, one of the
second emission stages is connected to a second emission start line ( Figure 6, [0054] discloses for the first/odd-numbered emission drivers 150-11, please note the emission start signal ESP to the first emission stage. Likewise, for the second/even-numbered emission drivers 150-12, please note a different emission start signal ESP as well ),
each of the first emission stages, except the first emission stage connected to the first
emission start line, is connected to a first emission line of a previous first emission stage ( Figure 6. [0054] discloses EST(3) is connected to an output of EST(1), namely EM(1)/EL(1) ), and
each of the second emission stages, except the second emission stage connected to the
second emission start line, is connected to a second emission line of a previous second emission
stage ( Figure 6, [0054] discloses EST(4) is connected to an output of EST(2), namely EM(2)/EL(2) ),
the first emission stage is configured to receive a first emission control signal via the
first emission start line, the first emission control signal defines non-emission periods and
emission periods of the first pixel rows during a frame period ( Figure 6, [0054], [0021] discloses the odd-numbered emission driver 150-11 with a first stage EST(1) receiving an ESP signal along the shown start line, as well as ECLKS(1) (read as a first emission control signal). [0073] notes ECLKS(1) is applied based on ESP (read as via). Figure 3, [0054] shows SF1 for the odd-numbered emission stages, including emission and non-emission periods being defined by the low and high states. To clarify, [0045] discloses one frame 1F (read as the claimed frame period) which comprises SF1 and SF2 ),
the second emission stage is configured to receive a second emission control signal via
the second emission start line, the second emission control signal defines non-emission periods
and emission periods of the second pixel rows during the frame period ( Figure 6, [0054], [0021] discloses the even-numbered emission driver 150-11 with a first stage EST(2) receiving an ESP signal along the shown start line, as well as ECLKS(2) (read as a second emission control signal). [0073] notes ECLKS(2) is applied based on ESP (read as via). To clarify, EST(2) receives a second/separate ESP wiring as well. Figure 4, [0054] shows SF2 for the even-numbered emission stages, including emission and non-emission periods being defined by the low and high states. To clarify again, [0045] discloses one frame 1F (read as the claimed frame period) which comprises SF1 and SF2 ), and
pixels in at least one of the first pixel rows and the second pixel rows are configured to
emit light at any point in time during the frame period ( Figures 3 and 4 show during SF1 and SF2 which make up 1F and pixels emit light, in conjunction with the emission drivers, during at least one of SF1 and SF2 ); but
In may not explicitly teach “a turn-off level of the first emission control signal and a turn-off level of the second emission control signal never overlap temporally during the frame period.”
In does teach: Figure 3 and 4 show the periods for SF1 and SF2, which correspond to the odd and even-numbered emission drivers. Please note the distinct periods, i.e. lack of overlap.
To emphasize on this, multiple emission control signals, Kang teaches of a pixel circuit with multiple OLED elements, ( Kang, Figure 10, [0113] ). Notably, each OLED element is controlled by a different emission control signal, with OLED1 being controlled by EMT and OLED2 being controlled by EMB. This is similar in sense to In who teaches of multiple OLEDs being controlled by different emission control signals. Furthermore, Kang teaches in Figure 11, [0115] of the on/off periods for EMB and EMT and it is seen the turn-off levels of these (as evidenced by the ON/OFF denotations for the associated OLEDs) never overlap temporally during the frame period. To clarify, when one OLED is emitting, the other is not and this lack of overlap is evident. As combined with In, who already teaches of alternate driving of emission drivers in Figures 3 and 4 (alternate meaning non-overlap here), an explicit turn-off level for the emission signals is taught.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date o the invention, to implement the alternating of emission signals, as taught by Kang, with the motivation that only one OLED would emit at a time, preventing left-right reversal, ( Kang, [0082] ).
7. Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over In et al. ( US 2021/0166635 A1 ) and Kang ( US 2019/0103060 A1 ), as applied to Claim 1, further in view of Lim et al. ( US 2022/0309998 A1 ).
In teaches in Claim 3:
The display device according to claim 1, wherein the first emission stages are connected to a first emission clock line ( Figure 6, [0073] discloses first emission clock signals ECLKS(1) are applied to the first/odd-numbered 150-11 ),
the second emission stages are connected to a second emission clock line ( Figure 6, [0074] discloses the second emission clock signals ECLKS(2) are applied to the second/even-numbered 150-12 ); but
In may not explicitly teach “pulses of a first emission clock signal applied to the first emission clock line and pulses of a second emission clock signal applied to the second emission clock line do not overlap each other.”
However, in the same field of endeavor, displays with emission drivers, Lim of an emission driver 14b, also with a plurality of emission stages EST11-EST14, etc, ( Lim, Figure 16, [0253] ). Notably, this embodiment has a plurality of emission clock lines ECLK1-ECLK4, which turn on and off the stages. Notably, Lim teaches in Figure 17, [0120] that these signals do not overlap each other and are turned on and off at particular times. For reference, please note Figure 9, [0145] which discloses a description of the various timings, such as t1b, t3b, etc, and how and when these clock lines are applied. As combined with In, timings of the emission clock lines can be implemented.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the timings of controlling the emission stages, as taught by Lim, with the motivation that the non-overlap allows for individual control of different stages, ideal for In’s two different groups, ( Lim, [0120] ).
In teaches in Claim 4:
The display device according to claim 3, wherein one of the first scan stages is connected to a first scan start line, one of the second scan stages is connected to a second scan start line ( Figure 8, [0081] discloses SST(1), one of the odd-numbered scan stages, is connected to scan start signal SOSP and SS(1)/SL(1). Likewise, [0084] discloses SST(2), one of the even-numbered scan stages, is connected to scan start signal SESP and SS(2)/SL(2) ),
each of the first scan stages, except the first scan stage connected to the first scan start line, is connected to a first scan line of a previous first scan stage ( Figure 8, [0081] discloses each of the odd-numbered scan stages are connected to a scan line of a previous stage, as shown ), and
each of the second scan stages, except the second scan stage connected to the second scan start line, is connected to a second scan line of a previous second scan stage. ( Figure 8, [0081] discloses each of the even-numbered scan stages are connected to a scan line of a previous stage, as shown )
In teaches in Claim 5:
The display device according to claim 4, wherein the first scan stages are connected to a first scan clock line ( Figure 8, [0083] discloses first clock signals SCLKS1() connected to the odd-numbered stages ),
the second scan stages are connected to a second scan clock line ( Figure 8, [0084] discloses second clock signals SCLKS2() connected to the even-numbered stages ), and
pulses of a first scan clock signal applied to the first scan clock line and pulses of a second scan clock signal applied to the second scan clock line do not overlap each other. ( In, Figure 3, [0046] shows SOSP and SESP, as well as SS(1) and SS(2), which do not overlap with each other. Furthermore, Lim, Figures 4 and 11, [0186] discloses first scan clock signals CK1 and CK3 as well as second scan clock signals CK2 and CK4, akin to In’s SCLK(1) and SCLKS(2). Figure 11 shows no overlap between the various clock signals )
In and Lim teach in Claim 6:
The display device according to claim 5, wherein the first emission clock signal and the first scan clock signal have the same waveform. ( In teaches of square waveforms for all signals, as shown in the various timing diagrams. Lim teaches of a similar concept in Figure 11, which shows CK1-CK4 having the same waveform as ECLK1 and ECLK2. Furthermore, Figures 12 and 13 show variations in the length, further rendering this as a design choice issue as one of ordinary skill in the art would be able to design the duration of the signals )
In teaches in Claim 7:
The display device according to claim 5, wherein the second emission clock signal and the second scan clock signal have the same waveform. ( In teaches of square waveforms for all signals, as shown in the various timing diagrams. Lim teaches of a similar concept in Figure 11, which shows CK1-CK4 having the same waveform as ECLK1 and ECLK2. Furthermore, Figures 12 and 13 show variations in the length, further rendering this as a design choice issue as one of ordinary skill in the art would be able to design the duration of the signals )
Response to Arguments
8. Applicant’s arguments considered, but are respectfully moot in view of new grounds of rejection(s).
Please note the updated rejection in light of the claim amendments, focusing on Kang. As a result, Applicant’s arguments are moot at this time.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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