DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, 18, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2018/0190197) in view of Ma et al. (US 2021/0335230).
In regard to claim 1, Chang et al. teach a pixel comprising: a first switching element including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node (DT); a third switching element including a control electrode which receives a writing gate signal (Scan (n)), a first electrode which receives a data voltage (Vdata) and a second electrode connected to the first node (DTG); a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node (C1); a second capacitor connected to the fourth node (C2)); a fourth switching element which receives an initialization gate signal and connected to the fourth node (T2); a light emitting element which emits light based on a driving current flowing thereto through the first switching element (OLED); and wherein the fourth switching element is connected to the second electrode of the first capacitor (connected at node DTG) and a first electrode of the second capacitor (connected through DT at node DTS. The entire device of Chang et al. is connected together) but does not teach a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node and a second electrode connected to the second node.
Ma et al. teach a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node and a second electrode connected to the second node (element T2).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Chang et al. with the diode connected transistor of Ma et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Chang et al. with the diode connected transistor of Ma et al. because it would improved signal driving range and lead to more accurate control.
In regard to claim 2, Chang et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal (SCAN (n-1))); a first electrode which receives a first power voltage (Vref); and a second electrode connected to the fourth node (fig. 2, the entire device is connected together).
In regard to claim 3, Chang et al. teach wherein the second capacitor includes: a first electrode connected to the fourth node; and a second electrode connected to the fifth node (fig. 2 the entire device is connected together).
In regard to claim 4, Chang et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the second node (C2).
In regard to claim 5, Chang et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal (Scan (n-1)); a first electrode connected to the fifth node; and a second electrode connected to the fourth node (T2 the entire device is connected together).
In regard to claim 6, Chang et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the fifth node (C2).
In regard to claim 7, Chang et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the second node (C2).
In regard to claim 8, Chang et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal; a first electrode connected to the second node; and a second electrode connected to the fourth node (T2).
In regard to claim 9, Chang et al. teach a fifth switching element including a control electrode which receives an emission signal (T4 receives EM), a first electrode which receives a first power voltage (VDD) and a second electrode connected to the fifth node (fig. 2 the entire device is connected together).
In regard to claim 10, Chang et al. teach a sixth switching element including a control electrode which receives a light emitting element initialization gate signal (T3 receives SCAN (n-1)), a first electrode which receives an initialization voltage (Vref) and a second electrode connected to the third node (fig. 2, the entire device is connected together).
In regard to claim 11, Chang et al. teach a fifth switching element including a control electrode which receives an emission signal, a first electrode which receives a first power voltage and a second electrode connected to the fifth node (T4), wherein the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element and the sixth switching element are P-type transistors (paragraph 42 and fig. 2).
In regard to claim 18, Chang et al. teach a seventh switching element including a control electrode which receives a second initialization gate signal (T3 is a separate transistor and receives a separate signal than T2), a first electrode which receives a reference voltage (Vref) and a second electrode connected to the first node (the entire device is connected together).
In regard to claims 20 and 21, Chang et al. and Ma et al. teach all the elements of claims 20 and 21 (see claim 1 rejection above) including an electronic apparatus comprising: a display panel including a pixel (Chang et al. fig. 1); a gate driver which outputs a gate signal to the pixel (Chang et al. element 103); a data driver which outputs a data voltage to the pixel (Chang et al. element 102) a driving controller which controls the gate driver and the data driver (Chang et al. element 110); and a processor which outputs input image data and an input control signal (Chang et al. paragraph 55, host system).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Ma et al. further considered with Kusunoki et al. (US 2024/0188330).
In regard to claim 12, Chang et al. and Ma et al. teach all the elements of claim 12 except wherein breakdown voltages of the first switching element and the sixth switching element are greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element and the fifth switching element.
Kusunoki et al. teach wherein breakdown voltages of the first switching element and the sixth switching element are greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element and the fifth switching element (paragraph 127, Kusunoki et al. teach using transistors with high breakdown voltages only for a few transistors).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Chang et al. and Ma et al. with the different transistors as shown in Kusunoki et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Chang et al. and Ma et al. with the different transistors as shown in Kusunoki et al. because the high-breakdown OS transistors of Kusunoki et al. achieve stable operation in high voltage driving situations.
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Ma et al. further considered with Huang et al. (US 2023/0146078).
In regard to claim 13, Chang et al. teach a fifth switching element including a control electrode which receives an emission signal, a first electrode which receives a first power voltage and a second electrode connected to the fifth node (T4) but neither Chang et al. nor Ma et al. teach wherein the first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element are P-type transistors, and wherein the sixth switching element is an N-type transistor.
Huang et al. teach wherein the first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element are P-type transistors, and wherein the sixth switching element is an N-type transistor (fig. 1 and paragraph 52, Huang et al. teach the initialization circuit contains n-type transistors and the rest of the transistors are p-type).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Chang et al. and Ma et al. with the different transistors as shown in Huang et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Chang et al. and Ma et al. with the different transistors as shown in Huang et al. because transistors of different types have different advantages (see Huang et al. paragraph 39 discussion on the advantages of n-type igzo transistors). One of ordinary skill in the art would recognize the use of different transistors in the display circuit would allow the customization based on parameters such as power usage, charge time and transistor mobility.
Response to Arguments
Applicant's arguments filed 12/18/25 have been fully considered but they are not persuasive. Applicant argues on page 12 that claims 1, 20 and 21 are amended to include the fifth switching element originally found in claims 14-16 and 19. This feature has not been added to the filed amended claims.
Applicant continues to argue on page 13 that the prior art fails to teach the fourth switching element connected in the manner required by the amended claims. The prior art does not teach the fourth transistor directly connected in the claimed manner; however, the entire device of Chang et al. is connected together. The limitation “connected” only requires the elements to be in the same device.
Allowable Subject Matter
Claims 14-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: in regard to claims 14-16 and 19, the prior art fails to teach or make obvious the timings of the gate signals in combination with the claim’s other features.
In regard to claim 17, the prior art fails to teach or make obvious the claimed relationship in combination with the claim’s other features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
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