Prosecution Insights
Last updated: August 18, 2026
Application No. 18/976,719

PIXEL, DISPLAY APPARATUS INCLUDING THE SAME AND DISPLAY APPARATUS INCLUDING THE SAME

Non-Final OA §103
Filed
Dec 11, 2024
Priority
Feb 26, 2024 — RE 10-2024-0027599
Examiner
HALEY, JOSEPH R
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
897 granted / 1133 resolved
+17.2% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
1165
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
57.5%
+17.5% vs TC avg
§102
23.9%
-16.1% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1133 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 2019/0304364) in view of Ma et al. (US 2021/0335230). In regard to claim 1, Xiao et al. teach a pixel comprising: a first switching element including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node (TD); a third switching element including a control electrode which receives a writing gate signal (T3 receives GATE), a first electrode which receives a data voltage (DATA) and a second electrode connected to the first node (N1. T3 is connected to the first node N1 through the capacitor C2); a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node (C2 connected to N1 and node below VDD); a second capacitor connected to the fourth node (C1 connected to VDD); a fourth switching element which receives an initialization gate signal (T2 and RST) and is directly connected to the fourth node (connected to node VDD); a light emitting element which emits light based on a driving current flowing thereto through the first switching element (OLED); and wherein the fourth switching element is connected to the second electrode of the first capacitor and a first electrode of the second capacitor (RST connected to C1 and C2) but does not teach a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node and a second electrode connected to the second node. Ma et al. teach a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node and a second electrode connected to the second node (element T2). The two are analogous art because they both deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiao et al. with the diode connected transistor of Ma et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Chang et al. with the diode connected transistor of Ma et al. because it would improved signal driving range and lead to more accurate control. In regard to claim 2, Xiao et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal (RST); a first electrode which receives a first power voltage (VDD); and a second electrode connected to the fourth node (T2 is connected to the entire device). In regard to claim 3, Xiao et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the fifth node (fig. 2, the capacitors of Xiao et al. are connected to all the nodes of the device). In regard to claim 4, Xiao et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the second node (fig. 2, the capacitors of Xiao et al. are connected to all the nodes of the device). In regard to claim 5, Xiao et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal (RST); a first electrode connected to the fifth node; and a second electrode connected to the fourth node (fig. 2, the elements of Xiao et al. are connected to all the nodes of the device). In regard to claim 6, Xiao et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the fifth node (fig. 2, the capacitors of Xiao et al. are connected to all the nodes of the device). In regard to claim 7, Xiao et al. teach wherein the second capacitor includes: the first electrode connected to the fourth node; and a second electrode connected to the second node (fig. 2, the capacitors of Xiao et al. are connected to all the nodes of the device). In regard to claim 8, Xiao et al. teach wherein the fourth switching element includes: a control electrode which receives the initialization gate signal (RST); a first electrode connected to the second node; and a second electrode connected to the fourth node (fig. 2, the elements of Xiao et al. are connected to all the nodes of the device). In regard to claim 9, Xiao et al. teach a fifth switching element including a control electrode which receives an emission signal (T4 receives EM), a first electrode which receives a first power voltage (T4 receives VDD when TD is active) and a second electrode connected to the fifth node (fig. 2, the elements of Xiao et al. are connected to all the nodes of the device). In regard to claim 10, Xiao et al. teach a sixth switching element including a control electrode which receives a light emitting element initialization gate signal (T5 receives RST), a first electrode which receives an initialization voltage (INIT) and a second electrode connected to the third node (fig. 2, the elements of Xiao et al. are connected to all the nodes of the device). In regard to claim 11, Xiao et al. teach a fifth switching element including a control electrode which receives an emission signal (T4 receives EM), a first electrode which receives a first power voltage (T4 receives VDD when TD is active) and a second electrode connected to the fifth node (fig. 2, the elements of Xiao et al. are connected to all the nodes of the device), wherein the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element and the sixth switching element are P-type transistors (fig. 2 and paragraph 13). Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. in view of Ma et al. further considered with Kusunoki et al. (US 2024/0188330). In regard to claim 12, Xiao et al. and Ma et al. teach all the elements of claim 12 except wherein breakdown voltages of the first switching element and the sixth switching element are greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element and the fifth switching element. Kusunoki et al. teach wherein breakdown voltages of the first switching element and the sixth switching element are greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element and the fifth switching element (paragraph 127, Kusunoki et al. teach using transistors with high breakdown voltages only for a few transistors). The three are analogous art because they all deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiao et al. and Ma et al. with the different transistors as shown in Kusunoki et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiao et al. and Ma et al. with the different transistors as shown in Kusunoki et al. because the high-breakdown OS transistors of Kusunoki et al. achieve stable operation in high voltage driving situations. Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. in view of Ma et al. further considered with Huang et al. (US 2023/0146078). In regard to claim 13, Xiao et al. teach a fifth switching element including a control electrode which receives an emission signal, a first electrode which receives a first power voltage and a second electrode connected to the fifth node (T4) but neither Xiao et al. non Ma et al. teach wherein the first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element are P-type transistors, and wherein the sixth switching element is an N-type transistor. Huang et al. teach wherein the first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element are P-type transistors, and wherein the sixth switching element is an N-type transistor (fig. 1 and paragraph 52, Huang et al. teach the initialization circuit contains n-type transistors and the rest of the transistors are p-type). The three are analogous art because they all deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiao et al. and Ma et al. with the different transistors as shown in Huang et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiao et al. and Ma et al. with the different transistors as shown in Huang et al. because transistors of different types have different advantages (see Huang et al. paragraph 39 discussion on the advantages of n-type igzo transistors). One of ordinary skill in the art would recognize the use of different transistors in the display circuit would allow the customization based on parameters such as power usage, charge time and transistor mobility. Claim 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. in view of Ma et al. further considered with Son et al. (US 2023/0070020). In regard to claim 18, Xiao et al. and Ma et al. teach all the elements of claim 18 except a seventh switching element including a control electrode which receives a second initialization gate signal, a first electrode which receives a reference voltage and a second electrode connected to the first node. Son et al. teach a seventh switching element including a control electrode which receives a second initialization gate signal, a first electrode which receives a reference voltage and a second electrode connected to the first node (Fig. 1 T4. Son et al. teach a transistor that is used to initialize the drive transistor). The three are analogous art because they all deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiao et al. and Ma et al. with the initialization transistor of Son et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiao et al. and Ma et al. with the initialization transistor of Son et al. because the initialization of Son et al. would allow for the compensation of threshold voltage and improve display accuracy. Claims 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. in view of Ma et al. further considered with Kasahara et al. (US 2018/0175071). In regard to claims 20 and 21, Xiao et al. teaches a display panel including a pixel (fig. 1 and paragraph 2) but neither Xiao et al. nor Ma et al. teach a gate driver which outputs a gate signal to the pixel; a data driver which outputs a data voltage to the pixel; a driving controller which controls the gate driver and the data driver; and a processor which outputs input image data and an input control signal. Kasahara et al. teach a gate driver which outputs a gate signal to the pixel (element 23); a data driver which outputs a data voltage to the pixel (element 27); a driving controller which controls the gate driver and the data driver (element 22); and a processor which outputs input image data and an input control signal (element 21). The three are analogous art because they all deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiao et al. and Ma et al. with the controllers of Kasahara et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiao et al. and Ma et al. with the controllers of Kasahara et al. the controllers of Kasahara et al. would allow the device of Xiao et al. and Ma et al. to accurately display different images. Allowable Subject Matter Claims 14-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for allowance: in regard to claims 14-16 and 19, the prior art fails to teach or make obvious the timings of the gate signals in combination with the claim's other features. In regard to claim 17, the prior art fails to teach or make obvious the claimed relationship in combination with the claim's other features. Conclusion Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance." Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH R HALEY/Primary Examiner, Art Unit 2621
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Prosecution Timeline

Dec 11, 2024
Application Filed
Sep 18, 2025
Non-Final Rejection mailed — §103
Dec 18, 2025
Response Filed
Feb 13, 2026
Final Rejection mailed — §103
Apr 08, 2026
Response after Non-Final Action
May 11, 2026
Request for Continued Examination
May 12, 2026
Response after Non-Final Action
Jul 02, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
86%
With Interview (+7.2%)
2y 5m (~8m remaining)
Median Time to Grant
High
PTA Risk
Based on 1133 resolved cases by this examiner. Grant probability derived from career allowance rate.

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