Prosecution Insights
Last updated: October 02, 2026
Application No. 18/977,022

ADAPTIVE ERROR HANDLING FOR A WIDE RANGE OF HIGH-RELIABILITY ERROR RATES

Final Rejection §103
Filed
Dec 11, 2024
Priority
Jan 10, 2024 — provisional 63/619,558
Examiner
MERANT, GUERRIER
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1106 granted / 1247 resolved
+33.7% vs TC avg
Minimal -2% lift
Without
With
+-2.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
1272
Total Applications
across all art units

Statute-Specific Performance

§101
8.9%
-31.1% vs TC avg
§103
45.4%
+5.4% vs TC avg
§102
15.1%
-24.9% vs TC avg
§112
17.4%
-22.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1247 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2, 4-9, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 9,189,333 B2 to Wu et al. ("Wu"), and further in view of Gunnam et al., US 8,607,115 B2 (“Gunnam”)). Claim 1: Wu teaches a method comprising: reading, by a processing device, a codeword from a memory device (e.g., col. 5, ll. 6-13 shows that "read data from a flash memory using a plurality of different read voltages"; col. 6, ll. 10-18; Fig. 7 step 702. See also col. 1, ll. 57-60); determining whether the codeword contains errors (e.g., As per col. 3, ll. 5-14, "a page read sometimes fails... ECC decoding is unable to correct all erroneous bits"; col. 6, ll. 18-25; Fig. 8 block 804); and responsive to the determining that the codeword contains errors, obtaining a first decoding parameter (e.g., Wu teaches generating soft input information (LLR values) used as decoding parameters when errors are detected. As per col. 1, ll. 54-63, "log likelihood ratio or similar ECC decoder soft input information... generated from decision patterns"; col. 4, ll. 36-44 conceptually shows that logic elements including LLR generating logic 220. Upon error detection, Wu performs a read retry using adjusted voltages to generate new LLRs, in col. 12, ll. 40-45; Fig. 8 blocks 808-812), wherein the first decoding parameter includes a first likelihood set (e.g., col. 11, ll. 48-60 shows generating numerical values/LLRs from decision patterns; col. 12, ll. 10-18 shows numerical values provided to soft-decoding ECC logic as LLRs. See also col. 7, ll. 39-50 shows computing weighted sums of decision values to generate LLRs); performing a decoding operation with the first decoding parameter (e.g., Wu teaches providing generated LLR values to soft-decoding ECC logic to attempt decoding. Col. 4, ll. 35-44 shows that LLR generating logic provides numerical values to soft-decoding ECC logic; Fig. 7 step 708 shows "input numerical values to soft-decoding ECC logic"; col. 13, ll. 5-8); responsive to determining that the decoding operation did not correct the errors of the codeword (e.g., Wu teaches read retry when decoding fails. Col. 12, ll. 1-15 shows that "if a read error occurs... read retry logic initiates another read"; Fig. 8 decision block 806 shows that if read error occurred, proceed to block 808; col. 3, ll. 5-14 shows that common method for responding to page read failure is "retry" or "read retry"), obtaining a second decoding parameter, wherein the second decoding parameter includes a second likelihood set (e.g., Wu generates new LLR values after performing another read with a different reference voltage. As per col. 6, ll. 20-35, using multiple reference voltages to read same cell generates different decision patterns and corresponding LLRs; Fig. 8 steps 808-814, shows (change reference voltage, read again, compute numerical values from decision patterns. Wu explicitly shows different LLR sets for different numbers of reads. See Fig. 9 shows LLR sets for 2 reads {2,0,-2} vs. 3 reads {3,1,-1,-3}); and performing the decoding operation with the second decoding parameter (e.g. Wu performs ECC decoding again after generating new LLR values. Fig. 8 step 814 shows that after generating new LLRs, the method proceeds to block 804 to perform soft decoding; col. 12, ll. 10-20). Wu does not teach that performing the decoding operation comprises initializing variable nodes with the first likelihood set and iteratively exchanging messages between the variable nodes and check nodes, wherein the first transformation set includes a scalar value and an offset value, and wherein the scalar value and the offset value are applied to messages passed from the check nodes to the variable nodes. Furthermore, Wu generates LLR values via weighted sums (col. 7, ll. 39-50) but does not explicitly disclose transforming likelihood values using quantization/scaling parameters as a distinct "transformation set." However, Gunnam teaches transforming LLR values through quantization and scaling using parameters β (scalar) and γ (offset). See Section 4 ("floating-point LLRs are quantized by two steps... q(x) = |β × x / min(x) + γ|"); Eq. (5) (quantization transformation formula) and Page 10 (LLR quantization discussion). Gunnam further teaches that β amplifies small LLRs to preserve precision and γ ensures non-zero LLRs during decoding (Section 4, Fig. 6). These constitute a "transformation set." Furthermore, Wu recomputes LLR values but does not explicitly disclose transforming likelihood values using quantization/scaling parameters as a distinct "transformation set" that varies between decoding attempts. However, Gunnam teaches an LDPC decoder in which each row of the parity-check matrix corresponds to a check node and each column corresponds to a variable node (e.g., col. 5, lines 6-9). Gunnam further teaches that the LDPC decoder receives soft values, such as LLRs, corresponding to bits of the codeword (e.g., col. 4, lines 15-18; col. 9, lines 54-55) and iteratively decodes the codeword using a message-passing algorithm (e.g. col. 2, lines 13-15; col. 4, lines 12-14). Besides, Gunnam teaches that, during the first decoding iteration, the initial soft values are used in place of prior variable-node Q messages (e.g. col. 4, lines 21-25, col. 5, lines 24-27). Gunnam also states that an initial soft value corresponding to a variable node is used in generating the variable-node message (e.g. col. 5, lines 53-57). Therefore, Gunnam teaches “initializing variable nodes with the first likelihood set.” Gunnam further teaches that check-node units perform check-node updates and variable-node units perform variable-node updates in an iterative message-passing process (e.g., col. 4, lines 53-57; col. 5, lines 39-40). An iteration is completed after the check-node and variable-node updates are performed (e.g. col. 4, lines 12-14). Gunnam also teaches that Q messages are passed to the check-node units, which generate R check-node messages using a suitable check-node algorithm, such as offset min-sum (e.g. col. 4, lines 53-59). Gunnam expressly defines R as a message corresponding to an m-th check node and an n-th variable node (e.g., col. 5, lines 6-10), and further states that alpha represents a scaling factor; and beta represents an offset value (e.g. col. 4, lines 60, equations (1). The R messages produced by the check-node units are subsequently provided to the variable-node units (e.g., col. 5, lines 38-40). Accordingly, Gunnam teaches: “iteratively exchanging messages between the variable nodes and check nodes,” and “the first transformation set includes a scalar value and an offset value, and wherein the scalar value and the offset value are applied to messages passed from the check nodes to the variable nodes.” In particular, Gunnam’s scaling factor alpha reasonably corresponds to the claimed scalar value, its beta corresponds to the claimed offset value, and its R messages correspond to the messages passed from check nodes to variable nodes. Therefore, before the effective filing date of the claimed invention, a POSITA seeking to implement Wu’s disclosed LDPC soft-decoding ECC logic would therefore have had reason to employ Gunnam’s known LDPC message-passing technique as a predictable implementation of Wu’s decoder for the following reasons: Wu expressly teaches use of LDPC soft decoding and LLR soft-input information for correcting errors in flash-memory data, but does not specify the internal implementation of the LDPC decoder. And Gunnam teaches a known implementation of an LDPC decoder in which likelihood information is used during initialization, variable nodes and check nodes iteratively exchange messages, and check-node-to-variable-node messages are processed using a scaling factor and an offset value. Moreover, Gunnam explains that trapping sets may prevent an LDPC decoder from properly recovering the codeword and that different decoding techniques can be employed to improve error-floor performance and prevent incorrect convergence (e.g., col. 1, lines 33-45). As per claims 8 and 15, the claimed limitations are obvious for the same reasons as claim 1. Claim 2: Wu and Gunnam teach the method of claim 1, wherein the first likelihood set of the first decoding parameter is different from the second likelihood set of the second decoding parameter or the first transformation set of the first decoding parameter is different from the second transformation set of the second decoding parameter. For instance, Wu teaches different LLR sets for different read attempts. Fig. 9 shows different LLR sets for 2 reads (first attempt after error) versus 3 reads (second attempt after error). See also col. 6, ll. 20-35 (different reference voltages produce different decision patterns and corresponding LLRs). Section 5.2 and Fig. 10 show that different numbers of reference voltages constitute different parameters. As per claims 9 and 16, the limitations claimed are obvious for the same reasons as claim 2. Claim 4: Wu and Gunnam teach the method of claim 2, wherein each likelihood set includes a plurality of likelihood values and corresponds to a range of high reliability error rate (HRER) values. For instance, Wu teaches LLR sets comprising multiple values corresponding to different voltage regions (Figs. 3-6) and different reliability conditions. See col. 7-8 (decision patterns and corresponding LLR values for different voltage regions). And Gunnam teaches that different pages (MSB, CSB, LSB) have different reliability characteristics (Fig. 2) and that LLR values correspond to different reliability ranges. Section 2.1 discusses reliability variations among bit positions. As per claim 11, the limitations claimed are obvious for the same reasons as claim 4. As per claim 17, the claimed limitations are obvious for the same reasons as claims 2 and 4. Claim 5: Wu and Gunnam teach the method of claim 1, further comprising: responsive to determining that the decoding operation did not correct the errors of the codeword, determining whether a subsequent decoding parameter can be obtained; responsive to determining that a subsequent decoding parameter can be obtained, obtaining a third decoding parameter, wherein the third decoding parameter includes a third likelihood set and a third transformation set; and performing the decoding operation with the third decoding parameter. For instance, Wu explicitly teaches this iterative process. Wu teaches reading data in an nth instance using an nth reference voltage, determining (n+1)th decision patterns, and generating (n+1)th plurality of numerical values (col. 12, ll. 45-65; Fig. 8 iterative loop). Wu states: "if it is determined a read error occurred in the nth instance, then the step of determining a plurality of decision patterns includes determining an (n+1)th decision pattern" (col. 12, ll. 55-60). See also col. 13, ll. 1-5 (continuing until either no error occurs or maximum reads performed). As per claims 12 and 18, the claimed limitations are obvious for the same reasons as claim 5. Claim 6: Wu and Gunnam teach the method of claim 1, but fail comprising: responsive to determining that the decoding operation did not correct the errors of the codeword, determining whether a subsequent decoding parameter can be obtained; responsive to determining that a subsequent decoding parameter cannot be obtained, flagging the codeword as unreliable. However, Wu teaches read retry continues until either no error occurs or a maximum number of reads is performed (col. 13, ll. 1-5). Therefore, a PHOSITA would understand that when maximum retries are exhausted without success, the data would be flagged as unreliable. As per claims 13 and 19, the claimed limitations are obvious for the same reasons as claim 6. Claim 7: Wu and Gunnam teach the method of claim 1, further comprising: responsive to determining that the decoding operation corrected the errors of the codeword, returning the codeword. For instance, Wu teaches that if no error occurs, the controller continues normal operation (col. 12, ll. 25-30; Fig. 8, if no read error occurred, continue to operate in conventional manner). As per claims 14 and 20, the claimed limitations are obvious for the same reasons as claim 7. Claim(s) 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu and Gunnam as applied to claim 1 above, and further in view of Cui et al., "Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision," ACM Transactions on Design Automation of Electronic Systems, Vol. 27, No. 1, Article 5, September 2021 ("Cui1”). Claim 3: Wu and Gunnam teach the method of claim 2, but fail to teach that the first transformation set and the second transformation set includes a scalar value and an offset value and corresponds to a range of high reliability error rate (HRER) values. However, Cui explicitly teaches this limitation. Formulas (5) and (6) disclose transformation parameters β (beta) (scalar value) and γ (gamma) (offset value) used to convert floating-point LLRs to fixed-point LLRs. Section 4 states: "β and γ are two constants. In general, β is set to 1, and γ is to ensure that LLR ≠ 0 during the decoding process." Section 6.3 discusses optimizing β for different decoding scenarios. Figure 6 shows the impact of different β values on performance. Regarding "HRER values", Cui teaches that LLR optimization corresponds to reliability characteristics. Section 4 discusses preserving precision of small LLRs because the decoder is sensitive to them. Section 2.1 and Figure 2 show that different bits (MSB, CSB, LSB) have different reliability characteristics. Therefore, a person having ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to combine Wu's iterative read retry framework with Cui's LLR optimization and quantization techniques to improve decoding performance. Both references address the identical technical problem: inaccurate LLRs degrading LDPC decoding performance in NAND flash memory (Wu, col. 1, ll. 62-67; Cui, Section 1). Wu provides the framework for iterative reads and LLR generation upon error detection. And Cui provides the specific mechanism for optimizing those LLRs via quantization parameters that can be tailored to different decoding stages. Applying known optimization techniques (Cui) to a known iterative process (Wu) to achieve predictable improvements in error correction would have been obvious to a PHOSITA. The combination represents the integration of prior art elements according to known methods to yield predictable results, which is precisely the situation where obviousness is found under KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007). As per claim 10, the claimed limitations are obvious for the same reasons as claim 3. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUERRIER MERANT whose telephone number is (571)270-1066. The examiner can normally be reached Monday-Friday 8:00 Am - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/11/2026
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Prosecution Timeline

Dec 11, 2024
Application Filed
Mar 24, 2026
Non-Final Rejection mailed — §103
May 27, 2026
Interview Requested
Jun 05, 2026
Examiner Interview Summary
Jun 05, 2026
Applicant Interview (Telephonic)
Jun 23, 2026
Response Filed
Aug 13, 2026
Final Rejection mailed — §103
Sep 25, 2026
Interview Requested

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
86%
With Interview (-2.4%)
2y 1m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1247 resolved cases by this examiner. Grant probability derived from career allowance rate.

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