CTNF 18/977,477 CTNF 73587 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION In response to the Communications dated December 11, 2024, claims 1-20 are active in this application. Specification If there are cross-reference to related applications, please include the respective patent numbers, if known. Information Disclosure Statement The information disclosure statements filed December 11, 2024 have been considered. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1, the term "first time period" is used to define the timing of two different, potentially conflicting operations (computation and page operation). It is indefinite because it is not clear how the memory device manages both tasks simultaneously. In claim 2, the phrase "a timing associated with..." is extremely vague. It does not define what that timing is (e.g., within 1ns, simultaneously, interleaved). In claim 3, the claim requires that "during the second time period" the system performs: A "second processing-in-memory (PIM) computation" (which likely requires reading/writing data from cells), and "Another page operation" (e.g., a bank access or activation) on the same first bank. It is noted that a single bank cannot perform a specific "page operation" (such as activating a new row to change which data is accessible) while simultaneously performing a "PIM computation" using the data currently in that bank, as these operations often conflict or are mutually exclusive at the hardware level. In claim 8, the claim indicates the sets are different, but not how they are different (e.g., are they different layers? Claims 4-7 are rejected because they depend on the indefiniteness of the claims from which they depend. 07-34-01 Claims 9-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 9, the term "first time period" is used to define the timing of two different, potentially conflicting operations (computation and page operation). It is indefinite because it is not clear how the memory device manages both tasks simultaneously. In claim 11, the claim requires that "during the second time period" the system performs: A "second processing-in-memory (PIM) computation" (which likely requires reading/writing data from cells), and "Another page operation" (e.g., a bank access or activation) on the same first bank. It is noted that a single bank cannot perform a specific "page operation" (such as activating a new row to change which data is accessible) while simultaneously performing a "PIM computation" using the data currently in that bank, as these operations often conflict or are mutually exclusive at the hardware level. Claims 10 and 12-14 are rejected because they depend on the indefiniteness of the claims from which they depend. 07-34-01 Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 15, the phrase "capable of" is vague, broad, and ambiguous because it describes a potentiality rather than a structural limitation. It suggests the device might perform a function, rather than requiring it to actually perform it. In claim 15, the term "first time period" is used to define the timing of two different, potentially conflicting operations (computation and page operation). It is indefinite because it is not clear how the memory device manages both tasks simultaneously. In claim 17, the claim requires that "during the second time period" the system performs: A "second processing-in-memory (PIM) computation" (which likely requires reading/writing data from cells), and "Another page operation" (e.g., a bank access or activation) on the same first bank. It is noted that a single bank cannot perform a specific "page operation" (such as activating a new row to change which data is accessible) while simultaneously performing a "PIM computation" using the data currently in that bank, as these operations often conflict or are mutually exclusive at the hardware level. Claims 16 and 18-20 are rejected because they depend on the indefiniteness of the claims from which they depend. Claim Rejections- 35 U.S.C. § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. [US Patent # 11,139,033]. With respect to claim 1, Seo et al. disclose a method performed by a memory device [“a memory device employing processing in memory (PIM), may include a plurality of memory banks and a control circuit 130.” – col. 4, lines 55,65 (The patent specifically describes a DRAM-based PIM device performing internal operations.)] , the method comprising: performing, during a first time period and using a logic circuit that is coupled to at least two banks [“each of the computation circuits 115 a and 115 b may include an arithmetic logic unit (ALU), …. Each of the computation circuits 115 a and 115 b may perform an operation using data read from the memory bank 110 a or 110 b corresponding to the computation circuit 115 a and 115 b , and write a result of the operation back into the corresponding memory bank 110 a or 110 b. ” – col. 5, lines 25-45 (PIM-enabled bank structure where arithmetic logic unit (ALU) is shared or coupled across bank boundaries.)] , a first processing-in-memory computation using first data that had been read from a first bank of the at least two banks [“The GIO SA 340 may transfer the data read from the DRAM cell array 310 to multiply-accumulation units (MACSs) 350. The MACSs 350 may correspond to each of the computation circuit 115 a and the computation circuit 115 b of FIG. 1. The MACSs 350 may perform an operation using the data transmitted from the GIO SA 340 and output a result of the operation.” – col. 8, lines 1-10 ("MAC arithmetic mode" to perform computation while "read data from the memory banks" The logic circuit operates in parallel to bank access, allowing computation (e.g., PIM) on data sourced from a bank.)] ; and performing, during the first time period, a page operation on a second bank of the at least two banks [“in order to satisfy the maximum power consumption condition while concurrently performing the processing of the memory requests for the memory banks Bank 0 and Bank 7 and continuously the PIM operation by the memory banks Bank 2 to Bank 5, the PIM operation by the memory banks Bank 2 to Bank 5 may slow down “ – col. 10, lines 25-35] to enable the logic circuit to access second data that is stored within the second bank [“Each of the computation circuits 115 a and 115 b may perform an operation using data read from the memory bank 110 a or 110 b corresponding to the computation circuit 115 a and 115 b , and write a result of the operation back into the corresponding memory bank 110 a or 110 b.” - col. 5, lines 35-45] . Claim(s) 9 and 10is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. [US Patent # 11,139,033]. With respect to claim 9, Seo et al. disclose a memory device [fig. 1] comprising: a memory array comprising at least two banks [110 with 110a and 110b] ; a logic circuit coupled to the at least two banks [“each of the computation circuits 115a and 115b may include an arithmetic logic unit (ALU), …. Each of the computation circuits 115a and 115b may perform an operation using data read from the memory bank 110a or 110b corresponding to the computation circuit 115a and 115b, and write a result of the operation back into the corresponding memory bank 110a or 110b.” – col. 5, lines 25-45 (PIM-enabled bank structure where arithmetic logic unit (ALU) is shared or coupled across bank boundaries.)] and configured to perform, during a first time period, a first processing-in-memory computation using first data that had been read from a first bank of the at least two banks [“The GIO SA 340 may transfer the data read from the DRAM cell array 310 to multiply-accumulation units (MACSs) 350. The MACSs 350 may correspond to each of the computation circuit 115 a and the computation circuit 115 b of FIG. 1. The MACSs 350 may perform an operation using the data transmitted from the GIO SA 340 and output a result of the operation.” – col. 8, lines 1-10 ("MAC arithmetic mode" to perform computation while "read data from the memory banks" The logic circuit operates in parallel to bank access, allowing computation (e.g., PIM) on data sourced from a bank.)] ; and read and write circuitry [“Commands “All commands” are issued from the memory controller (e.g., all commands generally used in the existing DRAM, such as a read RD command, a write WR command, the activate ACT command, the precharge PRE command, etc.) and may indicate commands for notifying the start of slow-down of the PIM operation. “ – col. 12, lines 50-65 (The read/write circuits are used to move data between the DRAM cells and the processing elements (e.g., SRAM buffers, ALU logic) that handle the arithmetic (like addition or multiplication). )] configured to perform, during the first time period, a page operation on a second bank of the at least two banks [“in order to satisfy the maximum power consumption condition while concurrently performing the processing of the memory requests for the memory banks Bank 0 and Bank 7 and continuously the PIM operation by the memory banks Bank 2 to Bank 5, the PIM operation by the memory banks Bank 2 to Bank 5 may slow down “ – col. 10, lines 25-35] to enable the logic circuit to access second data that is stored within the second bank [“Each of the computation circuits 115 a and 115 b may perform an operation using data read from the memory bank 110 a or 110 b corresponding to the computation circuit 115 a and 115 b , and write a result of the operation back into the corresponding memory bank 110 a or 110 b.” - col. 5, lines 35-45] . With respect to claim 10, Seo et al. disclose the first bank is configured to be in an active state during the first time period; and the second bank is configured to be in an idle state during the first time period [“the memory bank including the computation circuit and capable of performing the PIM operation slows down the PIM operation, and “Pause” refers to a state in which the memory bank including the computation circuit and capable of performing the PIM operation pauses the PIM operation.” – fig. 5 and col. 9, lines 30-40] . Conclusion For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI. When responding to the Office action, Applicants are advised to provide the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M. Any inquiry of a general nature or relating to the status of this application. should be directed to the Group receptionist whose telephone number is (571) 272-1650. /MICHAEL T TRAN/Primary Examiner, Art Unit 2827 May 11, 2026 Application/Control Number: 18/977,477 Page 2 Art Unit: 2827 Application/Control Number: 18/977,477 Page 3 Art Unit: 2827 Application/Control Number: 18/977,477 Page 4 Art Unit: 2827 Application/Control Number: 18/977,477 Page 5 Art Unit: 2827 Application/Control Number: 18/977,477 Page 6 Art Unit: 2827 Application/Control Number: 18/977,477 Page 7 Art Unit: 2827 Application/Control Number: 18/977,477 Page 8 Art Unit: 2827 Application/Control Number: 18/977,477 Page 9 Art Unit: 2827
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