DETAILED ACTION
1. Claims 1-27 are pending in this application filed on December 11, 2024. This Office Action is responsive to Applicant’s response (“the Response”) filed on August 25, 2026, in response to the Office Action issued on June 10, 2026. In the Response, Applicant amended claims 9, 16, and cancelled claims 10-11, 17-18. Claims 1-9, 12-16, and 19-27 are pending.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
3. Claims 9 and 16 have been amended. Applicant requests reconsideration of the rejection of these claims because Stave does not recite the amended limitations of claims 9 and 16. However, the claims are rejected because Bain teaches the added limitations of claim 9 as shown below.
4. Regarding claims 1 and 26, Applicant argues that chip select signals lasting two clock cycles do not teach the second active pulse as claimed. According to Applicant, “A person of ordinary skill in the art would understand that a pulse is a transient change in the amplitude of a signal form a baseline value to a higher or lower value, followed by a rapid return to the base line value. The mere assertion of a signal for more than one cycle, as disclosed in Stave, is not equivalent to a pulse.” This is not a persuasive argument, because Applicant’s characterization of an active pulse of a chip select signal is contrary to what a person of ordinary skill in the art would understand. Chip select signals work on voltage levels, not on a transition between two voltage levels. Thus, a chip select signal is active when its voltage level is high, not when the voltage level transitions from low to high, as Applicant’s argument implies. Two CS1 “active pulses” shown in FIG. 3 of the specification show two transitions per “active pulse” because they are spaced apart by two clock cycles. When these “active pulses” are applied for two consecutive clock cycles, they would look like a single pulse lasting for two clock cycles. Likewise, a chip select signal lasing two clock cycles is at least equivalent to two active pulse signals (i.e., one active pulse per clock cycle). If the novelty of Applicant’s memory device is a chip select procedure that depends on an “active pulse” with transient changes in the amplitude of the signal instead of the voltage level of the signal, as Applicant appears to be arguing, the claimed memory device would indeed be patentable because no other memory devices require an “active pulse” with transient changes in the signal amplitude for chip select function. All known memory devices use voltage levels of chip select signals, not transitions of signals between voltage levels.
Double Patenting – Non-Statutory
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
6. Claims 1-9, 12-16, and 19-27 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 and 14-28 of copending application no. 18/977,543 (“the ‘543 application”).
Claims 1-9, 12-16, and 19-27 are anticipated by claims 1-12 and 14-28 of the ‘543 application.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1, 3-4, 9, and 26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. No. 2019/0155544 (“Stave”).
9. With respect to claim 1, Stave discloses a system comprising:
a first memory rank (see FIG. 1, 150 and paragraph [0022]);
a second memory rank (see FIG. 1, 150 and paragraph [0022]); and
a controller (FIG. 4, 430) configured to:
provide a first chip select signal to the first memory rank (FIG. 2, CS_A 230, see paragraph [0024]);
provide a second chip select signal to the second memory rank(FIG. 2, CS_B 240, see paragraph [0024]) ; and
provide a command (FIG. 2, RD command) and an active pulse of the first chip select signal to the first memory rank to cause a target operation to be performed (FIG. 2, see channel 250, RD operation), and provide the command and a first active pulse of the second chip select signal to the second memory rank (see paragraph [0023], chip select pulse for the non-targeted portion for the first clock cycle), and further to provide a second active pulse of the second chip select signal (chip select pulse for the second clock cycle) to the second memory rank to cause a non-target operation to be performed that is different from the target operation (FIG. 2, channel 260, ODT operation; see also paragraphs [0023]-[0025]).
10. With respect to claim 3, Stave discloses the system of claim 1, wherein the first memory rank is configured to determine whether the first memory rank is a target memory rank based on the active pulse of the first chip select signal and the second memory rank is configured to determine whether the second memory rank is the target rank based on the active pulses of the second chip select signal (see FIG. 2 and paragraph [0024]. “A dedicated chip select terminal for each portion (e.g., CS_A 230 and CS_B 240) can be used to provide an indication to each portion whether it is targeted or non-targeted for communication,”).
11. With respect to claim 4, Stave discloses the system of claim 1, wherein the first memory rank and the second memory rank are configured to perform the respective target operation and non-target operation in parallel (see FIG. 2, RD 251 and ODT 261).
12. With respect to claim 26, see the rejection of claim 1 above.
13. Claims 1-9, 12-16, and 19-27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. No. 2016/0028395 (“Bains”).
14. With respect to claim 1, Bains discloses a system comprising:
a first memory rank (see FIG. 1, rank 130-0);
a second memory rank (FIG. 1, rank 130-(N-1)); and
a controller (FIG. 2, memory controller 210) configured to:
provide a first chip select signal to the first memory rank (FIG. 1, enable/select signals for rank 130-0);
provide a second chip select signal to the second memory rank(FIG. 1, enable/select signals for rank 130-(N-1)) ; and
provide a command (see FIG. 4A, see command column, WRITE-1 command for example) and an active pulse of the first chip select signal (FIG. 4, H value for CS pin) to the first memory rank to cause a target operation to be performed (paragraph see [0046]), and provide the command and a first active pulse of the second chip select signal to the second memory rank (see paragraph [0029], “In one embodiment, on Write the logic triggers the memory devices of the target rank to engage ODT, as well as one other rank to suppress reflection,” Accessing one other rank to engage ODT requires active CS signal), and further to provide a second active pulse of the second chip select signal to the second memory rank to cause a non-target operation to be performed that is different from the target operation (see paragraph [0030], “the memory device can be configured to change the ODT setting for a period of time equal to an expected duration of a memory access transaction.”, CS pin can be active for at least two cycles of WRITE-1 command. See also paragraph [0045]).
15. With respect to claim 2, Bains discloses the system of claim 1, wherein the command comprises an activate command (FIG. 4, ACTIVATE-1 command, see Abstract, a memory access command triggers ODT change in other non-target ranks. Activate command is a memory access command to open a rank for access).
16. With respect to claim 3, Bains discloses the system of claim 1, wherein the first memory rank is configured to determine whether the first memory rank is a target memory rank based on the active pulse of the first chip select signal and the second memory rank is configured to determine whether the second memory rank is the target rank based on the active pulses of the second chip select signal (see paragraph [0033], “every memory device of every memory rank can determine if it is part of the target rank.”, the second memory device can determine that it is selected for non-target operation based on active CS signal).
17. With respect to claim 4, Bains discloses the system of claim 1, wherein the first memory rank and the second memory rank are configured to perform the respective target operation and non-target operation in parallel (see Abstract).
18. With respect to claim 5, Bains discloses, the system of claim 1, wherein the non-target operation comprises at least one of termination impedance (ZQ) calibration start (see Abstract, FIG. 4B, and paragraphs [0053]-[0054]), ZQ calibration latch, data strobe (DQS) oscillator start, DQS oscillator stop, manual error check and scrub (ECS), refresh, refresh management (RFM), precharge, or power down entry.
19. With respect to claim 6, Bains discloses the system of claim 1, wherein the target operation comprises an operation to activate a row for a subsequent access operation (see the rejection of claim 2 above).
20. With respect to claim 7, Bains discloses the system of claim 1, wherein the command comprises a precharge command or a refresh command (FIG 4., REFRESH (ALL/PER BANK) command).
21. With respect to claim 8, Bains discloses, the system of claim 1, wherein the second memory rank is configured to determine the non-target operation based on at least one bit in the command or a setting in a mode register of the second memory rank (see paragraph [0044], “In one embodiment, the memory controller selectively triggers ODT on any given device based on decoding Write command.”).
22. With respect to claims 9, 16, 21, and 26, see the rejection of claims 1 and 8 above.
23. With respect to claims 15 and 24, see the rejection of claim 8 above.
24. With respect to claims 12 and 19, see the rejection of claim 7 above.
25. With respect to claims 13, 20, 22, 25, and 27, see the rejection of claim 5 above.
26. With respect to claims 14 and 23, see the rejection of claim 6 above.
Conclusion
27. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992
Prosecution Insights