DETAILED ACTION
This action is responsive to the following communications: the Application filed December 11, 2024, and the information disclosure statement (IDS) filed December 11, 2024, April, 15, 2026 and July 17, 2026.
Claims 1-31 are pending. Claims 1, 19 and 25 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 11, 2024, April, 15, 2026 and July 17, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 5 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martin et al. (US 2007/0002646).
Regarding independent claim 1, the claimed limitation(s) of column redundancy circuitry in multi-bank memory device is a well-known technology for a type of memory for its purpose. For support, of the above asserted facts, see for example, Martin et al. disclose a memory, comprising:
a plurality of banks (e.g., FIG. 1: 131A-131D), each bank being configured to repair at least one defect in response to a decoded redundancy address for the bank (FIG. 2: 101, and accompanying disclosure, e.g., para 0032-0034); and
a redundancy address decoder configured to decode a redundancy address for each bank into the decoded redundancy address for the bank (e.g., FIGS. 1-2 and accompanying disclosure, e.g., para. 0038).
Regarding claim 2, which depends from claim 1, Martin et al. disclose a serializer configured to serialize the decoded redundancy address into a serialized decoded redundancy address (e.g., FIG. 3 along with FIGS. 1-2 and accompanying disclosure, e.g., para. 0037: … defective memory cell address … serial-load, parallel-output register …; further this address scheme is a well-known technology, see for example, Kohara et al. (US 2009/0044045), e.g., para. 0057-0059).
Regarding claim 3, which depends from claim 1, Martin et al. disclose the serializer is a parallel-in-serial-out (PISO) shift register (see FIG. 4 and accompanying disclosure, e.g., para. 0041: … a parallel-to-seral transmission …).
Regarding claim 4, which depends from claim 2, Martin et al. disclose each bank is further configured to deserialize the serialized decoded redundancy address in a scan chain (see FIGS. 2-4 and accompanying disclosure; further this address scheme is a well-known technology, see for example, Kohara et al. (US 2009/0044045), FIG. 3 and accompanying disclosure).
Regarding claim 5, which depends from claim 4, Martin et al. disclose the scan chain comprises a shift register including a serial chain of flip-flops (FIGS. 4-6 and accompanying disclosure).
Regarding claim 13, which depends from claim 2, Martin et al. disclose the redundancy address for each bank is a column redundancy address for the bank, and wherein the redundancy address decoder comprises a column redundancy address decoder configured to decode the column redundancy address for each bank into a decoded column redundancy address for the bank (e.g., FIGS. 1-3 and accompanying disclosure; further it’s a well-known technology).
Claims 19 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morzano (US 2019/0055895).
Regarding independent method claim 19 and its device claim 25, the claimed limitation(s) of column redundancy circuitry in multi-bank memory device is a well-known technology for a type of memory for its purpose. For support, of the above asserted facts, see for example, Morzano discloses a column redundancy address decoding method, comprising:
decoding, in a shared column redundancy address decoder (FIGS. 1A-1C: 120), a first column redundancy address for a first bank (140(0)) in a memory to provide a first decoded column redundancy address to the first bank (see e.g., FIGS. 1A-1C, and accompanying disclosure); and
decoding, in the shared column redundancy address decoder (FIGS. 1A-1C: 120), a second column redundancy address for a second bank (140(1)) in the memory to provide a second decoded column redundancy address to the second bank (see e.g., FIGS. 1A-1C, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9, 11, 17, 19 and 25 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Martin et al. (US 2007/0002646) in view of Morzano (US 2019/0055895).
Regarding claim 6, Martin et al. teach the limitations of claim 1.
Martin et al. further teach a non-volatile memory configured to store a non-volatile address for each bank; and a central decoder configured to decode the non-volatile address for each bank into the redundancy address for each bank (e.g., FIGS. 1-4 and accompanying disclosure).
Martin et al. do explicitly disclose a central decoder.
However, a central decoder in multi-bank memory circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Morzano, e.g., FIG. 1A: 120, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Morzano to the teaching of Martin et al. such that a memory, as taught by Martin et al., utilizes a central decoder, as taught by Morzano, for the purpose of controlling multi-banks with centralized control circuit; further these conventional technology are well established in the art of the memory devices.
Regarding claim 7, Martin et al. and Morzano, as combined, teach the limitations of claim 6.
Morzano further teaches the central decoder is further configured to decode the non-volatile address for each bank into a redundancy enable signal for the bank (e.g., FIG. 2A and accompanying disclosure; further it is a well-known technology, see Kohara US (2009/0044045), e.g., FIG. 1 and para. 0037; and Ohtani (US 2004/114449)), FIG. 1 and para. 0098.
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Morzano for the same purpose of controlling multi-banks with centralized control circuit.
Regarding claim 8, Martin et al. and Morzano, as combined, teach the limitations of claim 6.
Morzano further teaches the non-volatile memory comprises a fuse memory and the central decoder comprises a fuse decoder, and wherein the non-volatile address for each bank is a fuse address for each bank (see FIGS. 1A-C: 110 and FIGS 2A-2B: 210, and accompanying disclosure, e.g., para. 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Morzano for the same purpose of controlling multi-banks with centralized control circuit.
Regarding claim 9, Martin et al. and Morzano, as combined, teach the limitations of claim 8.
Morzano further teaches the fuse decoder is configured to decode fuse addresses for the plurality of banks in series (e.g., para. 0048).
Regarding claim 11, Martin et al. and Morzano, as combined, teach the limitations of claim 7.
Martin et al. further teach each bank includes a plurality of bitcells arranged into a plurality of columns and the at least one defect is a defective column in the plurality of columns (e.g., FIGS. 1-2).
Regarding claim 17, Martin et al. and Morzano, as combined, teach the limitations of claim 11.
Martin et al. and Morzano do explicitly disclose each column includes a pair of bit lines.
However, a pair of bit lines such as bit line and bit line bar in a memory device is a well-known technology.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize bit line pairs because these conventional technology are well established in the art of the memory devices.
Regarding independent method claim 19 and its device claim 25, Martin et al. teach a column redundancy address decoding method, comprising:
decoding, in a shared column redundancy address decoder, a first column redundancy address for a first bank in a memory to provide a first decoded column redundancy address to the first bank; and
decoding, in the shared column redundancy address decoder, a second column redundancy address for a second bank in the memory to provide a second decoded column redundancy address to the second bank (see e.g., FIGS. 1-2, and accompanying disclosure).
Martin et al. are silent with respect to a shared column redundancy address decoder.
However, a central decoder in multi-bank memory circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Morzano, e.g., FIG. 1A: 120, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Morzano to the teaching of Martin et al. such that a memory, as taught by Martin et al., utilizes a central decoder, as taught by Morzano, for the purpose of controlling multi-banks with centralized control circuit; further these conventional technology are well established in the art of the memory devices.
Claim 10 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Martin et al. (US 2007/0002646) in view of Ohtani (US 2004/0114449).
Regarding claim 10, Martin et al. teach the limitations of claim 1.
Martin et al. do not explicitly disclose the redundancy address decoder comprises: a plurality of predecoders each configured to decode part of the redundancy address; and a final decoder configured to decode a combination of signals output from the plurality of predecoders to form the decoded redundancy address.
However, a pre-decoder in memory circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Ohtani teaches the deficiencies in e.g., FIG. 1, 30 and 30#, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Ohtani to the teaching of Martin et al. such that a memory, as taught by Martin et al., utilizes a pre-decoder, as taught by Ohtani, for the purpose of controlling multi-banks with efficient decoding circuit; further these conventional technology are well established in the art of the memory devices.
Claims 12 and 14-15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Martin et al. (US 2007/0002646) in view of Morzano (US 2019/0055895), further in view of Kohara et al. (US 2009/0044045).
Regarding claim 12, Martin et al. and Morzano, as combined, teach the limitations of claim 11.
Martin et al. do not explicitly disclose bank’s plurality of columns is arranged into a plurality of multiplexed groups of columns and the defective column is included within a defective multiplexed group of columns.
However, a plurality of multiplexed groups of columns is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Kohara et al. (US 2009/0044045), e.g., FIG. 2 and accompanying disclosure, e.g., para 0046-0047.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize multiplexed groups of column and defective column because these conventional technology are well established in the art of the memory devices
Regarding claim 14, Martin et al., Morzano and Kohara et al., as combined, teach the limitations of claim 12.
Martin et al. and Kohara et al. further teach each bank further includes a plurality of input/output circuits and at least one redundant group of multiplexed columns, and wherein each bank is configured to respond to an assertion of the redundancy enable signal for the bank by a shifting of a correspondence between the input/output circuits and the plurality of multiplexed groups of columns to form a shifted correspondence that includes the at least one redundant group of multiplexed columns (e.g., Martin, FIGS. 1-4 and accompanying disclosure; and Kohara, e.g., FIG. 2 and accompanying disclosure, e.g., para 0046-0047).
Regarding claim 15, Martin et al., Morzano and Kohara et al., as combined, teach the limitations of claim 14.
Kohara et al. further teach the at least one redundant group of multiplexed columns comprises a pair of redundant columns (e.g., FIG. 2 and accompanying disclosure, e.g., para. 0046).
Claims 16 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Martin et al. (US 2007/0002646).
Regarding claim 16, Martin et al. teach the limitations of claim 1.
Martin et al. do not explicitly the at least one defect comprises a pair of defective columns.
However, a pair of bit lines such as bit line and bit line bar in a memory device is a well-known technology.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize bit line pairs because these conventional technology are well established in the art of the memory devices
Regarding claim 18, Martin et al. teach the limitations of claim 1.
Martin et al. do not explicitly the memory is included within an integrated circuit within a cellular telephone.
However, the claimed limitation is a well-known technology.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory device in IC within cell phones these conventional technology are well established in the art of the memory devices
Regarding dependent claims 20-24 and 26-31 are rejected for the same reason set forth above as applied to claims 1-18.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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