DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication filed 05/08/2026. There are a total of 20 claims pending in the application, no claims have been added, amended or canceled.
Response to Remarks:
3. Applicant Remarks have been fully considered but they are not persuasive. In page 1-2 appears applicant argues subject matters which are not included in the claim. For example, page 1 of the remarks recites
“dynamic capacity devices (DCDs) are logical memory devices supported by standard of compute express link (CXL), where the capacity of a dynamic capacity device attached via compute express link (CXL) to a host system can be adjusted or changed without restarting the host system and/or without restarting the computing system containing the host system and the memory device”.
However, even if the above subject matter were included in claim, Lee teaches the subject matter. Regarding rejection of independent claim 1, a portion of limitation of claims highlighted as shown below:
“configuring, based on the power efficiency level and in response to the request without restarting, operations of the compute express link fabric in routing memory access requests having memory addresses in the logical memory device; and receiving, in the compute express link fabric after the configuring, the memory access requests. (emphasis added)”
The Examiner respectfully disagrees. For Example, Fig. 1 shows a computing system comprising host processors connected, via CXL interface, CXL pool memory device 110. The pool memory device 110 includes a plurality memory 150s (e.g., see par. 0053). The plurality of memories 150 may be partitioned into a predetermined number of logical devices (e.g., par. 0055). A controller configured to allocate a memory area of the plural memories for a plurality of logical devices, track an available memory capacity of each logical device, and cut off power supplied to an unused logical device among the plurality of logical devices (e.g., par. 0041).
“controller can be configured to, in response to a first request input from the at least one external device, migrate data from the first memory to the second memory and cut off the power supplied to the first memory” (par. 0026, emphasis added).
Lee further teaches:
“[0101] Referring to FIG. 8, among the plurality of memory cards 450A, 450B, 450C, 450D, the first memory card 450A and the second memory card 450B are being used, and the third memory card 450C and the fourth memory card 450B are not being used. The memory card 450D may not be used. The controller 430 may cut off power supplied to the third memory card 450C and fourth memory card 450D which are not used. Through this procedure, power consumption in the pooled memory device 410 can be reduced, as well as resource usage efficiency of data infrastructure can be improved.” (Emphasis added)
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al. “Lee” (US 2024/0126469 A1).
4. Regarding claim 9, Lee teaches or suggests:
“A system (e.g., Fig.1), comprising: a compute express link fabric having a controller;” (e.g., Fig. 1, ¶ 055, controller 130 may perform data communication with the interconnect device 180 through a Compute Express Link (CXL) interface). The controller 130, shown in Fig. 1, comprises a CXL controller.
“a plurality of memory devices connected to the compute express link fabric. and a plurality of host processors connected to the compute express link fabric.” (e.g., Fig.1, ¶ 0055). The CXL or pooled memory device 110 comprises plurality of memory devices 150, as shown in Fig. 1, connected via a CXL interface and a CXL switch to a plurality of hos CPU’s or processor (e.g., host 102A and host 102B in Fig. 1). Lee does not expressly teach “power efficiency level”. The disclosure by Chou teaches “power efficiency level”.
In summary, the examiner respectfully submits that Lee alone or in combination with Chou teach or renders obvious all limitations included in rejected claims. Accordingly, Examiner maintains his position.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 10-11, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. “Lee” (US 2024/0126469 A1) in view of Chou “Chou” (US 2005/0097377 A1).
5. regarding claim 1, Lee teaches or suggests:
“A method (e.g., ¶ 0063), comprising: receiving, in a compute express link fabric, a request identifying (e.g., Fig. 1, ¶ 0055, The controller 130 may perform data communication with the interconnect device 180 through a Compute Express Link (CXL) interface…the controller 130 may distribute data input/output operations transmitted from the plurality of host systems 102A, 102B to the pooled memory device 110 and manage power supplied to the plurality of memories 150 in the pooled memory device 110…The controller 130 can control the at least one power supply to supply or cut off power to each of the plurality of memories 150; ¶ 0050, plurality of memories 150 may be partitioned into a predetermined number of logical devices; ¶ 0053, When the pooled memory device 110 includes a CXL-based Dynamic Random Access Memory (DRAM) device; ¶ 0118, Referring to FIGS. 8 and 11, the controller 430 in the multi-logical device 410 may receive requests transmitted from the plurality of host processors 104A, 104B through the switch device 480. For example, the first host processor 104A may transmit a first request for cutting off the power supplied to the first logical device to the multi-logical device 410 in order to reduce power consumption. Before the controller 430 cuts off the power supplied to the first logical device, valid data stored in the first logical device (e.g., data stored in the memory area currently allocated to and used by the at least one host processor 104A, 104B) can be migrated to the second logical device. The controller 430 may update the address range table or add new mapping information for the migrated data and then transfer the updated address range table to the at least one host processor 104A, 104B. Thereafter, the controller 430 may cut off power supplied to the first logical device). The host requests are received/transmitted via CXL interface to the pooled memory device. Comprises a logical identifier or logical addresses for logical memory device (or a logical device). The fist request address or identifier identifies a first logical memory device and a second logical memory device in order to reduce power. Before the controller 430 cuts off power, migrates valid data from the first logical device to another or a second logical device. The controller changes or updates the mapping table and sends a copy of updated mapping table to the hosts. The power cut-off the logical device reduces power consumption and increases the power efficiency of the memory device.
“configuring, based on the (e.g., Abstract; ¶ 0025, a controller coupled to an interconnect device configured to provide, to at least one external device, the plural memory devices as logical devices, the controller configured to track available memory capacities of the first memory and the second memory and cut off power supplied to an unused memory; Fig. 11, ¶ 0115, migrating data used in a first logical device to a second logical device in response to an address of a first logical device transmitted together with the first request … transferring an address in the second logical unit for migrated data to the at least one host processor, and cutting off power supplied to the first logical device).
and receiving, in the compute express link fabric after the configuring, the memory access requests.” (e.g., claim 1, a controller coupled to an interconnect device configured to provide, to at least one external device, the plural memory devices as plural logical devices; claim 2, the controller is configured to, in response to a first request input from the at least one external device, migrate data from the first memory to the second memory and cut off the power supplied to the first memory; claim 7). Lee teaches a system comprising one or more host processor(s) connected to, via one or more Compute Express Link (CXL), pooled memory device. The pooled memory device include a plurality memory devices. The plurality of memory devices comprise a plurality or multiple logical memory devices or logical devices (e.g., Figs. 1-10 and the corresponding descriptions. Lee further teaches that system configured to track or monitor available capacity of logical devices in order to efficiently utilize resources and reduce power consumption of logical device (e.g. see paragraph [0119] and Fig. 11 of Lee). However, Lee does not expressly teach while Chou discloses:
“power efficiency level” (e.g., ¶ 0013, the power-saving mode can be directly used to cut off memory power and reach a higher power efficiency level).
Disclosures by Lee and Chou are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and Method for Controlling a Pooled Memory Device or a Memory Expander taught by Lee to include the power efficiency level disclosed by Chou.
The motivation for including the power efficiency level as taught by Lee is to reduce the frequency clock in power saving or refresh mode to reduce some power consumption and or cut off power to memory device and reach a higher power efficiency level (e.g., see pars. 0010-0013 of Chou).
Therefore, it would have been obvious to combine teaching of Chou with Lee to obtain the invention as specified in the claim.
6. Regarding claim 17, Lee teaches or suggests:
A non-transitory computer storage medium storing instructions which, when executed by a controller of a compute express link fabric, cause the controller to perform a method (e.g., ¶ 0133), comprising: receiving a request identifying (e.g., Fig. 1, ¶ 0055, The controller 130 may perform data communication with the interconnect device 180 through a Compute Express Link (CXL) interface…the controller 130 may distribute data input/output operations transmitted from the plurality of host systems 102A, 102B to the pooled memory device 110 and manage power supplied to the plurality of memories 150 in the pooled memory device 110…The controller 130 can control the at least one power supply to supply or cut off power to each of the plurality of memories 150; ¶ 0118, Referring to FIGS. 8 and 11, the controller 430 in the multi-logical device 410 may receive requests transmitted from the plurality of host processors 104A, 104B through the switch device 480. For example, the first host processor 104A may transmit a first request for cutting off the power supplied to the first logical device to the multi-logical device 410 in order to reduce power consumption). The host requests are received/transmitted via CXL interface to the pooled memory device, comprise logical identifiers or logical addresses to logical device. The first request address or identifier indicates a first logical memory device. The controller configured to cut off power to the first logical memory device (e.g., see claims 1-3 of Lee). Cutting the power to a logical memory device, reduces the power consumption and increases the power efficiency of the memory device.
“and customizing, based on the power efficiency l(e.g., ¶ 0036, a method for operating a memory expander can include receiving a first request transmitted through an interconnect device from at least one external device; migrating data from a first logical device to a second logical device in response to an address of the first logical device which is transmitted along with the first request; transmitting, to the at least one external device, an address of a location in which the migrated data is stored within the second logical device; and cutting off power to the first logical device when the first logical device becomes unused by the at least one external device; ¶ 0118, Referring to FIGS. 8 and 11, the controller 430 in the multi-logical device 410 may receive requests transmitted from the plurality of host processors 104A, 104B through the switch device 480…the first host processor 104A may transmit a first request for cutting off the power supplied to the first logical device to the multi-logical device 410 in order to reduce power consumption. Before the controller 430 cuts off the power supplied to the first logical device, valid data stored in the first logical device (e.g., data stored in the memory area currently allocated to and used by the at least one host processor 104A, 104B) can be migrated to the second logical device. The controller 430 may update the address range table or add new mapping information for the migrated data, and then transfer the updated address range table to the at least one host processor 104A, 104B. Thereafter, the controller 430 may cut off power supplied to the first logical device). Lee does not expressly recite “customizing”, but Applicant defines/describes customizing as to change mapping based or as a result of receiving a request to identify power efficiency level (e.g., see claim 10 of the instant application). However, Lee teaches a first request to identify or address a first logical memory device in order to cut-off the power in order to reduce power consumption. However, before the power cut-off, valid data from the first logical device migrated to a second logical memory device. After migration of the valid data is completed, the power to the first logical device is cut-off. The controller changes or update mapping table (e.g., because of migration or change in location of data) and controller sends a copy of updated mapping table to the host processor (e.g., par. [0118] of Lee). The power consumption of the memory devices is highly reduced due to power cu-off. However, Lee does not expressly teach while Chou discloses:
“power efficiency level” (e.g., ¶ 0013, the power-saving mode can be directly used to cut off memory power and reach a higher power efficiency level). The motivation for combining is based on the same rational presented above with respect to the independent claim 1.
7. Regarding claim 2, Lee further teaches:
“determining, by the compute express link fabric, memory resources in a plurality of memory devices connected to the compute express link fabric;” (e.g., Fig. 1, ¶ 0053, the interconnect device 180 can support or provide versatility and scalability of resources through the pooled memory device 110 to overcome resource limitations of the plurality of host systems 102A, 102B. For example, interconnect device 180 may include a Compute Express Link (CXL) switch. Herein, the Compute Express Link (CXL) is an interface provided to efficiently utilize different types of devices in high-performance computing systems; ¶ 0126, The memory expander or the pooled memory device can monitor or track a memory area in plural logical devices, which is used by at least one host processor or computing system).
“and routing the memory access requests through the compute express link fabric to the memory devices to access the memory resources;” (e.g., ¶ 0036, a method for operating a memory expander can include receiving a first request transmitted through an interconnect device from at least one external device).
“wherein the configuring includes changing a mapping between the memory addresses and the memory resources.” (e.g., ¶ 0100, change or update mapping information regarding the migrated data or allocation information of the 5 G area).
8. Regarding claims 3 and 11, Lee further teaches:
“wherein the memory devices include a first memory device and a second memory device having difference power efficiency levels;” (e.g., ¶ 0026, the controller can be configured to, in response to a first request input from the at least one external device, migrate data from the first memory to the second memory and cut off the power supplied to the first memory; ¶ 0026, The controller can be configured to, in response to a first request input from the at least one external device, migrate data from the first memory to the second memory and cut off the power supplied to the first memory). The first memory with its power cut-off and the second memory storing data (e.g., active memory) having different power efficiency level.
“and the changing includes changing a mapping destination of a region of the memory addresses between the first memory device and the second memory device.” (e.g., ¶ 0100, change or update mapping information regarding the migrated data or allocation information of the 5 G area).
Chou discloses: “power efficiency level” (e.g., ¶ 0013, the power-saving mode can be directly used to cut off memory power and reach a higher power efficiency level).
9. Regarding claim 10, Lee further teaches:
“wherein the controller is configured to receive a request identifying a power efficiency (e.g., Figs 8 and 11 and their corresponding text descriptions).
Chou discloses: “power efficiency level” (e.g., ¶ 0013, the power-saving mode can be directly used to cut off memory power and reach a higher power efficiency level). See also the Examiner notes regarding rejection of the independent claim 17.
10. Regarding claim 18, Lee further teaches:
“wherein the method further comprises changing a mapping between the memory addresses and memory resources in the memory devices allocated to implement the logical memory device, including changing, in response to the request, a mapping destination of a region of the memory addresses between a first memory device and a second memory device among the memory devices.” (e.g., ¶ 0036, a method for operating a memory expander can include receiving a first request transmitted through an interconnect device from at least one external device; migrating data from a first logical device to a second logical device in response to an address of the first logical device which is transmitted along with the first request; transmitting, to the at least one external device, an address of a location in which the migrated data is stored within the second logical device; and cutting off power to the first logical device when the first logical device becomes unused by the at least one external device; ¶ 0118, Referring to FIGS. 8 and 11, the controller 430 in the multi-logical device 410 may receive requests transmitted from the plurality of host processors 104A, 104B through the switch device 480…the first host processor 104A may transmit a first request for cutting off the power supplied to the first logical device to the multi-logical device 410 in order to reduce power consumption. Before the controller 430 cuts off the power supplied to the first logical device, valid data stored in the first logical device (e.g., data stored in the memory area currently allocated to and used by the at least one host processor 104A, 104B) can be migrated to the second logical device. The controller 430 may update the address range table or add new mapping information for the migrated data, and then transfer the updated address range table to the at least one host processor 104A, 104B. Thereafter, the controller 430 may cut off power supplied to the first logical device).
Allowable Subject Matter
Claims 4-8, 12-16, and 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
11. The prior art of record does not teach or render obvious limitation(s):
“wherein the compute express link fabric is configured to change the mapping destination between the first memory device and the second memory device periodically to implement the power efficiency level identified in the request”, Recited in claims 4, 12, and 19. Clams 5-8, 13-16, and 20 are allowable at leased based on the claims 4, 12, and 19, respectively.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/HASHEM FARROKH/ Primary Examiner, Art Unit 2138
Prosecution Insights