DETAILED ACTION
1. This Office Action is responsive to a response filed for No. 18/978,186 on February 13, 2026. Please note Claims 1-20 are pending.
America Invents Act
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 13, 2026 has been entered.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang
( US 2020/0302870 A1 ) in view of Kang et al. ( US 2024/0021165 A1 ).
Jang teaches in Claim 1:
A driver including a plurality of stages ( Figure 2, [0054] discloses an emission controller driver 40 with a plurality of stages ), at least one stage of the plurality of stages comprising:
an input circuit that transfers an input signal to a first Q node in response to a first clock signal ( Figure 4, [0071] discloses an input circuit 410 which controls the voltage at node N4 (read as a first Q node) in response to CLK1 and transferring FLM );
a node separating circuit electrically connected between the first Q node and a second Q node ( Figure 4, [0088] discloses a second stabilizer 462 between N4 and N2 (read as a second Q node) and in particular, please interpret transistor M12 as the node separating circuit );
a node controlling circuit that controls a voltage of a QB node based on a voltage of the first Q node, a high gate voltage, a low gate voltage, the first clock signal, and a second clock signal ( Figure 4, [0119] discloses a first signal processor 430, second signal processor 440, second stabilizer 461, etc (read these three as a node controlling circuit, though this is not meant to be limiting) which controls a voltage at node N1 (read as a QB node) and this is based on N4, VDD, VSS, CLK1 and CLK2, as shown );
an output circuit that generates an output signal based on the voltage of the QB node, a voltage of the second Q node, the high gate voltage, and the low gate voltage ( Figure 4, [0068] discloses an output circuit 420 which outputs to terminal 104 in response to N1 and N2, VDD and VSS, as shown ); and
a boosting circuit that receives the voltage of the QB node, the high gate voltage, and the low gate voltage, and to boost the voltage of the second Q node to a boosted low level in case that the voltage of the second Q node becomes a low level ( Figure 4, [0080] discloses transistors M2, M3 and third capacitor C3 (read these elements as a boosting circuit). Please note M2 receives a voltage from N1, VDD, VSS and [0105] discloses supplying a low voltage to node N7 and on to node N2 (the interpreted second Q node) such that is can be maintained at a voltage (a 2-step low voltage) less than the voltage of VSS by coupling of the third capacitor C3 ),
wherein the node separating circuit includes a fourth transistor having a gate connected to the low gate voltage ( Figure 4, [0089] discloses transistor M12 having a gate connected to VSS ), and the boosting circuit includes a second transistor having a gate connected to the second Q node ( Figure 3, [0083] discloses transistor M3 having a gate connected to N2 ); but
Jang does not explicitly teach “a second terminal of the second transistor receives a same voltage as the gate of the fourth transistor, and each of the second terminal of the second transistor and the gate of the fourth transistor is directly connected to a low voltage input”.
Initially, Jang teaches in Figure 3 of M12 having a gate directly connected to VSS.
However, in the same field of endeavor, shift register circuits with an emphasis on output nodes, Kang teaches of a similar layout to Jang, ( Kang, Figure 8, [0115] ). Notably, Figure 8 shows transistor T8 (read as the claimed fourth transistor and akin to Jang’s M12) and transistor T5 (read as the claimed second transistor and akin to Jang’s M3). Please note Kang’s T8 has a gate connected to VGL (similar to Jang’s M12) and T5 has a second terminal also connected to VGL (modifying Jang’s M3). Please note Applicant’s boosting circuit 290 receives a VGH to node N1 and Kang teaches similar with regards to IN3 from VGH. As combined with Jang, the second terminal T5 of Kang is provided, also with a connection to VGL.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the connections of transistor T5 to VGL, as taught by Kang, with the motivation that the stabilizer circuit toggles between the low and high power supply, allowing for variable frame rate changes, ( Kang, [0004] ).
Jang and Kang teach in Claim 2:
The driver of claim 1, wherein the boosting circuit includes:
a first transistor that applies the high gate voltage to an internal node in response to the voltage of the QB node ( Figure 4, [0082] discloses transistor M2 coupled between VDD and node N7 (read as an internal node) ); and
a first capacitor electrically connected between the second Q node and the internal node ( Figure 4, [0099] discloses third capacitor C3 connected between N2 and N7 ), and
wherein the second transistor applies the low gate voltage to the internal node in response to the voltage of the second Q node. ( Please note the combination with Kang to teach of the transistor T5 as shown in Figure 8. This passes the low gate voltage to the interpreted node )
Jang teaches in Claim 3:
The driver of claim 2, wherein, in case that the voltage of the second Q node becomes the low level,
the first transistor is turned off in response to the voltage of the QB node such that the internal node is electrically separated from a line which transfers the high gate voltage, the second transistor is turned on in response to the voltage of the second Q node such that a voltage of the internal node is changed from the high gate voltage to the low gate voltage, and the first capacitor boosts the voltage of the second Q node from the low level to the boosted low level based on the voltage of the internal node changed from the high gate voltage to the low gate voltage. ( Figure 4, [0104]-[0105], [0110] disclose the operation, namely during first period t1 and second period t2. During these periods, M2 is toggled on and off and allows for the transfer of the low boost voltage to node N2 )
Jang teaches in Claim 4:
The driver of claim 2, wherein
the first transistor includes a gate electrically connected to the QB node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the internal node ( Figure 4, [0082] discloses transistor M2 has a gate electrically connected to N1, a first terminal receiving VDD and a second terminal electrically connected to node N7 ),
the second transistor further includes, a first terminal electrically connected to the internal node, and the second terminal of the second transistor receives the low gate voltage ( Figure 4, [0083] discloses M3 has a gate electrically connected to node N2, a first terminal electrically connected to N7 and a second terminal which receives VSS. As noted in [0105], a low voltage is applied to node N2 ), and
the first capacitor includes a first electrode electrically connected to the internal node, and a second electrode electrically connected to the second Q node. ( Figure 4, [0099] discloses capacitor C3 with a first electrode electrically connected to node N7 and a second electrode electrically connected to node N2 )
Jang teaches in Claim 5:
The driver of claim 1, wherein the input circuit includes:
a third transistor that transfers the input signal to the first Q node in response to the first clock signal. ( Figure 4, [0072] discloses transistor M1 which transfers the input FLM to node N4 in response to CLK1 )
Jang teaches in Claim 6:
The driver of claim 5, wherein the third transistor includes a gate which receives the first clock signal, a first terminal which receives the input signal, and a second terminal electrically connected to the first Q node. ( Figure 4, [0072] discloses M1 with a gate receiving CLK1, a first terminal receiving FLM and a second terminal electrically connected to node N4 )
Jang teaches in Claim 7:
The driver of claim 1, wherein the fourth transistor of the node separating circuit is turned on in response to the low gate voltage. ( Figure 4, [0089] discloses transistor M12 which is turned on by VSS )
Jang teaches in Claim 8:
The driver of claim 7, wherein the fourth transistor further includes, a first terminal electrically connected to the first Q node, and a second terminal electrically connected to the second Q node. ( Figure 4, [0089] discloses a gate of transistor M12 which receives VSS, a first terminal electrically connected to node N4 and a second terminal electrically connected to node N2 )
Jang teaches in Claim 9:
The driver of claim 1, wherein the node controlling circuit includes:
a fifth transistor that transfers the first clock signal to a first control node in response to the voltage of the first Q node ( Figure 4, [0084] discloses transistor M4-1 and M4-2 which transfers CLK1 to node N3 (read as a first control node) in response to the voltage at node N4 );
a sixth transistor that transfers the low gate voltage to the first control node in response to the first clock signal ( Figure 4, [0085] discloses transistor M5 transferring VSS to node N3 in response to CLK1 );
a seventh transistor electrically connected between the first control node and a second control node ( Figure 4, [0087] discloses transistor M11 which is electrically connected between node N3 and node N5 (read as a second control node) );
an eighth transistor that transfers the second clock signal to a third control node in response to a voltage of the second control node ( Figure 4, [0078] discloses transistor M6 which transfers CLK2 to node N6 (read as a third control node) in response to node N5 );
a second capacitor electrically connected between the second control node and the third control node ( Figure 4, [0076]-[0077] discloses a second capacitor C2 electrically connected between nodes N5 and N6 );
a ninth transistor that electrically connects the third control node to the QB node in response to the second clock signal ( Figure 4, [0079] discloses transistor M7 that is electrically connected to node N6 and node N1 and functions in response to CLK2 );
a third capacitor electrically connected between a line which transfers the high gate voltage and the QB node ( Figure 4, [0075] discloses capacitor C1 which is electrically connected between VDD and node N1 ); and
a tenth transistor that transfers the high gate voltage to the QB node in response to the voltage of the first Q node. ( Figure 4, [0074] discloses transistor M8 which transfers VDD in response to the voltage at node N1 )
Jang teaches in Claim 10:
The driver of claim 9, wherein
the fifth transistor includes a gate electrically connected to the first Q node, a first terminal electrically connected to the first control node, and a second terminal which receives the first clock signal ( Figure 4, [0084] discloses transistor M4-1 and M4-2 with a gate electrically connected to node N4, a first terminal electrically connected to node N3 and a second terminal which receives CLK1 ),
the sixth transistor includes a gate which receives the first clock signal, a first terminal electrically connected to the first control node, and a second terminal which receives the low gate voltage ( Figure 4, [0085] discloses transistor M5 with a gate that receives CLK1, a first terminal electrically connected to node N3 and a second terminal which receives VSS ),
the seventh transistor includes a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, and a second terminal electrically connected to the second control node ( Figure 4, [0087] discloses transistor M11 with a gate that receives VSS, a first terminal electrically connected to node N3 and a second terminal electrically connected to node N5 ),
the eighth transistor includes a gate electrically connected to the second control node, a first terminal electrically connected to the third control node, and a second terminal which receives the second clock signal ( Figure 4, [0078] discloses transistor M6 with a gate electrically connected to node N5, a first terminal connected to node N6 and a second terminal receiving CLK2 ),
the second capacitor includes a first electrode electrically connected to the second control node, and a second electrode electrically connected to the third control node ( Figure 4, [0076]-[0077] discloses capacitor C2 electrically connected to node N5 and a second terminal electrically connected to node N6 ),
the ninth transistor includes a gate which receives the second clock signal, a first terminal electrically connected to the QB node, and a second terminal which receives the third control node ( Figure 4, [0079] discloses transistor M7 with a gate that receives CLK2, a first terminal electrically connected to node N1 and a second terminal which receives the voltage at node N6 ),
the third capacitor includes a first electrode electrically connected to the line which transfers the high gate voltage, and a second electrode electrically connected to the QB node ( Figure 4, [0075] discloses capacitor C1 with a first electrode connected to VDD and a second electrode electrically connected to node N1 ), and
the tenth transistor includes a gate electrically connected to the first Q node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the QB node. ( Figure 4, [0074] discloses transistor M8 with a gate electrically connected to node N4, a first terminal which receives VDD and a second terminal electrically connected to node N1 )
Jang teaches in Claim 11:
The driver of claim 9, wherein the fifth transistor includes a plurality of sub-transistors electrically connected in series between the first control node and a line which transfers the first clock signal. ( Figure 4, [0084] discloses M4 has sub-transistors M4-1 and M4-2 electrically connected in series between node N3 and CLK1 )
Jang teaches in Claim 12:
The driver of claim 1, wherein the output circuit includes:
an eleventh transistor that outputs the high gate voltage as the output signal in response to the voltage of the QB node ( Figure 4, [0069] discloses transistor M9 outputting VDD in response to the voltage at node N1 ); and
a twelfth transistor that outputs the low gate voltage as the output signal in response to the voltage of the second Q node. ( Figure 4, [0070] discloses transistor M10 outputting VSS in response to the voltage at node N2 )
Jang teaches in Claim 13:
The driver of claim 12, wherein
the eleventh transistor includes a gate electrically connected to the QB node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to an output node at which the output signal is output ( Figure 4, [0069] discloses transistor M9 with a gate electrically connected to node N1, a first terminal receiving VDD and a second terminal connected to output terminal 104 ), and
the twelfth transistor includes a gate electrically connected to the second Q node, a first terminal electrically connected to the output node, and a second terminal which receives the low gate voltage. ( Figure 4, [0070] discloses transistor M10 with a gate electrically connected to node N2, a terminal electrically connected to output terminal 104 and a second terminal receiving VSS )
Jang teaches in Claim 14:
The driver of claim 1, wherein transistors included in the at least one stage are P-type metal-oxide-semiconductor (PMOS) transistors. ( [0090] discloses the transistors may be formed of a p-type transistor )
Jang teaches in Claim 15:
A driver including a plurality of stages ( Figure 2, [0054] discloses an emission controller driver 40 with a plurality of stages ), at least one stage of the plurality of stages comprising:
an input circuit that transfers an input signal to a first Q node in response to a first clock signal ( Figure 4, [0071] discloses an input circuit 410 which controls the voltage at node N4 (read as a first Q node) in response to CLK1 and transferring FLM );
a node separating circuit electrically connected between the first Q node and a second Q node ( Figure 4, [0088] discloses a second stabilizer 462 between N4 and N2 (read as a second Q node) and in particular, please interpret transistor M12 as the node separating circuit );
a node controlling circuit that controls a voltage of a QB node based on a voltage of the first Q node, a high gate voltage, a low gate voltage, the first clock signal, and a second clock signal ( Figure 4, [0119] discloses a first signal processor 430, second signal processor 440, second stabilizer 461, etc (read these three as a node controlling circuit, though this is not meant to be limiting) which controls a voltage at node N1 (read as a QB node) and this is based on N4, VDD, VSS, CLK1 and CLK2, as shown );
an output circuit that generates an output signal based on the voltage of the QB node, a voltage of the second Q node, the high gate voltage, and the low gate voltage ( Figure 4, [0068] discloses an output circuit 420 which outputs to terminal 104 in response to N1 and N2, VDD and VSS, as shown );
a first transistor including a gate electrically connected to the QB node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to an internal node ( Figure 4, [0082] discloses transistor M2 with a gate electrically connected to node N1, a first terminal receiving VDD and a second terminal electrically connectected to node N7 (read as an internal node) );
a second transistor including a gate electrically connected to the second Q node, a first terminal electrically connected to the internal node, and a second terminal which receives the low gate voltage ( Figure 4, [0083], [0105] discloses transistor M3 with a gate electrically connected to node N2, a first terminal electrically connected to node N7 and a second terminal which receives VSS. [0105] discloses transistor M3 being turned on and applying a low voltage to node N7 in response to N2. Clearly, this is in response to VSS ); and
a first capacitor including a first electrode electrically connected to the internal node, and a second electrode electrically connected to the second Q node ( Figure 4, [0099] discloses capacitor C3 with a first electrode electrically connected to node N7 and a second electrode electrically connected to node N2 ),
wherein the node separating circuit includes a fourth transistor having a gate ( Figure 4, [0089] discloses transistor M12 having a gate connected to VSS ); but
Jang does not explicitly teach wherein the node separating circuit includes a fourth transistor having a gate which receives a same voltage as the second terminal of the second transistor, and each of the second terminal of the second transistor and the gate of the fourth transistor is directly connected to a low voltage input”.
Initially, Jang teaches in Figure 3 of M12 having a gate directly connected to VSS.
However, in the same field of endeavor, shift register circuits with an emphasis on output nodes, Kang teaches of a similar layout to Jang, ( Kang, Figure 8, [0115] ). Notably, Figure 8 shows transistor T8 (read as the claimed fourth transistor and akin to Jang’s M12) and transistor T5 (read as the claimed second transistor and akin to Jang’s M3). Please note Kang’s T8 has a gate connected to VGL (similar to Jang’s M12) and T5 has a second terminal also connected to VGL (modifying Jang’s M3). Please note Applicant’s boosting circuit 290 receives a VGH to node N1 and Kang teaches similar with regards to IN3 from VGH. As combined with Jang, the second terminal T5 of Kang is provided, also with a connection to VGL.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the connections of transistor T5 to VGL, as taught by Kang, with the motivation that the stabilizer circuit toggles between the low and high power supply, allowing for variable frame rate changes, ( Kang, [0004] ).
Jang teaches in Claim 16:
The driver of claim 15, wherein the input circuit includes:
a third transistor including a gate which receives the first clock signal, a first terminal which receives the input signal, and a second terminal electrically connected to the first Q node ( Figure 4, [0072] discloses M1 with a gate receiving CLK1, a first terminal receiving FLM and a second terminal electrically connected to node N4 ),
the fourth transistor of the node separating circuit further includes:
a first terminal electrically connected to the first Q node, and a second terminal electrically connected to the second Q node ( Figure 4, [0089] discloses a gate of transistor M12 which receives VSS, a first terminal electrically connected to node N4 and a second terminal electrically connected to node N2 ),
the node controlling circuit includes:
a fifth transistor including a gate electrically connected to the first Q node, a first terminal electrically connected to a first control node, and a second terminal which receives the first clock signal ( Figure 4, [0084] discloses transistor M4-1 and M4-2 with a gate electrically connected to node N4, a first terminal electrically connected to node N3 and a second terminal which receives CLK1 );
a sixth transistor including a gate which receives the first clock signal, a first terminal electrically connected to the first control node, and a second terminal which receives the low gate voltage ( Figure 4, [0085] discloses transistor M5 with a gate that receives CLK1, a first terminal electrically connected to node N3 and a second terminal which receives VSS );
a seventh transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, and a second terminal electrically connected to a second control node ( Figure 4, [0087] discloses transistor M11 with a gate that receives VSS, a first terminal electrically connected to node N3 and a second terminal electrically connected to node N5 );
an eighth transistor including a gate electrically connected to the second control node, a first terminal electrically connected to a third control node, and a second terminal which receives the second clock signal ( Figure 4, [0078] discloses transistor M6 with a gate electrically connected to node N5, a first terminal connected to node N6 and a second terminal receiving CLK2 );
a second capacitor including a first electrode electrically connected to the second control node, and a second electrode electrically connected to the third control node ( Figure 4, [0076]-[0077] discloses capacitor C2 electrically connected to node N5 and a second terminal electrically connected to node N6 );
a ninth transistor including a gate which receives the second clock signal, a first terminal electrically connected to the QB node, and a second terminal which receives the third control node ( Figure 4, [0079] discloses transistor M7 with a gate that receives CLK2, a first terminal electrically connected to node N1 and a second terminal which receives the voltage at node N6 );
a third capacitor including a first electrode electrically connected to a line which transfers the high gate voltage, and a second electrode electrically connected to the QB node ( Figure 4, [0075] discloses capacitor C1 with a first electrode connected to VDD and a second electrode electrically connected to node N1 ); and
a tenth transistor including a gate electrically connected to the first Q node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the QB node ( Figure 4, [0074] discloses transistor M8 with a gate electrically connected to node N4, a first terminal which receives VDD and a second terminal electrically connected to node N1 ), and
the output circuit includes:
an eleventh transistor including a gate electrically connected to the QB node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to an output node at which the output signal is output ( Figure 4, [0069] discloses transistor M9 with a gate electrically connected to node N1, a first terminal receiving VDD and a second terminal connected to output terminal 104 ); and
a twelfth transistor including a gate electrically connected to the second Q node, a first terminal electrically connected to the output node, and a second terminal which receives the low gate voltage. ( Figure 4, [0070] discloses transistor M10 with a gate electrically connected to node N2, a terminal electrically connected to output terminal 104 and a second terminal receiving VSS )
Jang teaches in Claim 17:
An electronic device comprising:
a processor configured to provide input image data; and a display device configured to receive the input image data from the processor, and to display an image based on the input image ( Figure 1, [0067] discloses a variety of processors ),
the display device ( Figure 1, [0050] discloses a display device ) comprising:
a display panel including a plurality of pixels ( Figure 1, [0050]-[0051] discloses a pixel unit 10 with a plurality of pixels PX );
a data driver that provides data signals to the plurality of pixels ( Figure 1, [0053] discloses a data driver 30 for providing data signals );
a gate driver that provides gate signals to the plurality of pixels ( Figure 1, [0052] discloses a scan driver 20 for providing scan signals );
an emission driver that provides emission signals to the plurality of pixels ( Figure 1, [0054] discloses an emission driver 40 for providing emission control signals ); and
a controller that controls the data driver, the gate driver, and the emission driver at least by providing inputs to each of the data driver, the gate driver, and the emission driver ( Figure 1, [0055] discloses a timing controller 50 for providing various signals to the above drivers ), wherein
at least one of the gate driver and the emission driver includes a plurality of stages ( Figure 2, [0054] discloses the emission controller driver 40 with a plurality of stages ), and at least one stage of the plurality of stages includes:
an input circuit that transfers an input signal to a first Q node in response to a first clock signal ( Figure 4, [0071] discloses an input circuit 410 which controls the voltage at node N4 (read as a first Q node) in response to CLK1 and transferring FLM );
a node separating circuit electrically connected between the first Q node and a second Q node ( Figure 4, [0088] discloses a second stabilizer 462 between N4 and N2 (read as a second Q node) and in particular, please interpret transistor M12 as the node separating circuit );
a node controlling circuit that controls a voltage of a QB node based on a voltage of the first Q node, a high gate voltage, a low gate voltage, the first clock signal, and a second clock signal ( Figure 4, [0119] discloses a first signal processor 430, second signal processor 440, second stabilizer 461, etc (read these three as a node controlling circuit, though this is not meant to be limiting) which controls a voltage at node N1 (read as a QB node) and this is based on N4, VDD, VSS, CLK1 and CLK2, as shown );
an output circuit that generates an output signal based on the voltage of the QB node, a voltage of the second Q node, the high gate voltage, and the low gate voltage ( Figure 4, [0068] discloses an output circuit 420 which outputs to terminal 104 in response to N1 and N2, VDD and VSS, as shown ); and
a boosting circuit that receives the voltage of the QB node, the high gate voltage, and the low gate voltage, and to boost the voltage of the second Q node to a boosted low level in case that the voltage of the second Q node becomes a low level ( Figure 4, [0080] discloses transistors M2, M3 and third capacitor C3 (read these elements as a boosting circuit). Please note M2 receives a voltage from N1, VDD, VSS and [0105] discloses supplying a low voltage to node N7 and on to node N2 (the interpreted second Q node) such that is can be maintained at a voltage (a 2-step low voltage) less than the voltage of VSS by coupling ); and
wherein the node separating circuit includes a fourth transistor having a gate connected to the low gate voltage ( Figure 4, [0089] discloses transistor M12 having a gate connected to VSS ), and the boosting circuit includes a second transistor having a gate connected to the second Q node ( Figure 3, [0083] discloses transistor M3 having a gate connected to N2 ); but
Jang does not explicitly teach “a second terminal of the second transistor receives a same voltage as the gate of the fourth transistor, and each of the second terminal of the second transistor and the gate of the fourth transistor is directly connected to a low voltage input”
Initially, Jang teaches in Figure 3 of M12 having a gate directly connected to VSS.
However, in the same field of endeavor, shift register circuits with an emphasis on output nodes, Kang teaches of a similar layout to Jang, ( Kang, Figure 8, [0115] ). Notably, Figure 8 shows transistor T8 (read as the claimed fourth transistor and akin to Jang’s M12) and transistor T5 (read as the claimed second transistor and akin to Jang’s M3). Please note Kang’s T8 has a gate connected to VGL (similar to Jang’s M12) and T5 has a second terminal also connected to VGL (modifying Jang’s M3). Please note Applicant’s boosting circuit 290 receives a VGH to node N1 and Kang teaches similar with regards to IN3 from VGH. As combined with Jang, the second terminal T5 of Kang is provided, also with a connection to VGL.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the connections of transistor T5 to VGL, as taught by Kang, with the motivation that the stabilizer circuit toggles between the low and high power supply, allowing for variable frame rate changes, ( Kang, [0004] ).
Jang teaches in Claim 18:
The electronic device of claim 17, wherein the boosting circuit includes:
a first transistor that applies the high gate voltage to an internal node in response to the voltage of the QB node ( Figure 4, [0082] discloses transistor M2 coupled between VDD and node N7 (read as an internal node) ); and
a first capacitor electrically connected between the second Q node and the internal node ( Figure 4, [0099] discloses third capacitor C3 connected between N2 and N7 ); and
the second transistor applies the low gate voltage of the internal node in response to the voltage of the second Q node. ( Please note the combination with In to teach of the transistor M14 as shown in Figure 6. This passes the low gate voltage to the interpreted node )
Jang teaches in Claim 19:
The electronic device of claim 18, wherein, in case that the voltage of the second Q node becomes the low level, the first transistor is turned off in response to the voltage of the QB node such that the internal node is electrically separated from a line which transfers the high gate voltage, the second transistor is turned on in response to the voltage of the second Q node such that a voltage of the internal node is changed from the high gate voltage to the low gate voltage, and the first capacitor boosts the voltage of the second Q node from the low level to the boosted low level based on the voltage of the internal node changed from the high gate voltage to the low gate voltage. ( Figure 4, [0104]-[0105], [0110] disclose the operation, namely during first period t1 and second period t2. During these periods, M2 is toggled on and off and allows for the transfer of the low boost voltage to node N2 )
Jang and In teach in Claim 20:
The electronic device of claim 18, wherein
the first transistor includes a gate electrically connected to the QB node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the internal node ( Figure 4, [0082] discloses transistor M2 has a gate electrically connected to N1, a first terminal receiving VDD and a second terminal electrically connected to node N7 ),
the second transistor further includes, a first terminal electrically connected to the internal node, and the second terminal of the second transistor receives the low gate voltage ( Figure 4, [0083] discloses M3 has a gate electrically connected to node N2, a first terminal electrically connected to N7 and a second terminal which receives VSS. As noted in [0105], a low voltage is applied to node N2 ), and
the first capacitor includes a first electrode electrically connected to the internal node and a second electrode electrically connected to the second Q node. ( Figure 4, [0099] discloses capacitor C3 with a first electrode electrically connected to node N7 and a second electrode electrically connected to node N2 )
Response to Arguments
7. Applicant’s arguments considered, but are respectfully moot in view of new grounds of rejection(s).
Please note the updated rejection, notably the citation of Kang. As a result, Applicant’s arguments are moot at this time.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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