DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al (KR20220006360A with English translation in IDS).
Regarding Claim 1, Choi et al teaches an apparatus for three-dimensional (3D) parallelization for a heterogeneous GPU cluster (Fig. 5), comprising: memory in which at least one program is recorded; and a processor for executing the program, wherein the program generates initialization information based on GPU memory capacity in order to parallelize a model across multiple nodes constituting a heterogeneous GPU cluster, pipeline-parallelizes the model based on the multiple nodes using the
generated initialization information (Figs. 1-3, 5; Page 11, line 5- Page 13, line 3; Page 14, line 29- Page 16, line 22), and data/tensor-parallelizes layers of the model, which are allocated to each of the multiple nodes according to pipeline parallelization, based on GPUs mounted in the corresponding node. (Figs. 1-3, 5; Page 11, line 5- Page 13, line 3; Page 14, line 29- Page 16, line 22).
Regarding Claim 2, Choi et al teaches the apparatus wherein the multiple nodes include an equal number of GPUs mounted therein, and the number of GPUs is a power of 2 (Figs. 1-3).
Regarding Claim 11, the method Claim 11 is rejected for same reason as the apparatus Claim 1, since claim limitations are same in both claims.
Allowable Subject Matter
Claim 20 is allowed.
Claims 3-10, 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
None of the prior art, made of record, either singularly or in combination, teaches or fairly suggests the features presented in the limitations of Claim 20, such as “when there is a node to which layers having a memory requirement greater than a total amount of GPU memory of the node is allocated, reallocating part of the layers of the corresponding node to another node;
initially calculating a tensor parallelism degree and a data parallelism degree for each of the nodes; and setting a final tensor parallelism degree and a final data parallelism degree by aggregating values initially calculated for the respective nodes. ”, recited by Claim 20.
Examiner notes the current invention as disclosed in the independent claims is allowed in its entirety. Each and every limitation working together in concert realizes the current claimed invention’s novelty. No single limitation alone accomplishes the allowability of the inventive independent claim(s). Rather, each and every limitation of the claim(s) and their disclosed relationships are integral.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well.
It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
Examiner’s Note
Examiner has cited particular paragraphs/columns and line numbers or figures in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicant’s definition which is not specifically set forth in the claims.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIJAY SHANKAR whose telephone number is (571)272-7682. The examiner can normally be reached M-F 9 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VIJAY SHANKAR
Primary Examiner
Art Unit 2624
/VIJAY SHANKAR/Primary Examiner, Art Unit 2624
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