Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alrod et al. (US Pub # 2022/0206710).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Alrod et al. teach a method of programming a memory device, comprising the steps of: preparing a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184 where memory array includes block BLK_0…7 and wordline WL); in a selected memory block of the plurality of memory blocks, programming foggy data into the memory cells of a selected word line of the plurality of word lines in a first programming pass (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2006, 2401); in at least one parity memory block of the plurality of memory blocks, programming two bits of parity data; reading the foggy data of the memory cells of the selected word line of the selected memory block and reading the parity data of the at least one parity memory block to reconstruct user data (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2008, 2405, 2409); and performing a second programming pass on the selected word line of the selected memory block (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2012, 2421).
Even though Alrod et al. teach programming / storing parity data bit but silent exclusively about programming two bits of parity data. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Alrod et al. where two bits (0/1) data were generated and store / program in SLC memory (see specially Fig. 12, 16) in order to improve programming performance for the memory device (see paragraph 0006, 0178).
Regarding claim 2, Alrod et al. further teach, wherein the parity data is stored in a two-bits per memory cell storage format (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, especially Fig. 12, 16).
Regarding claim 3, Alrod et al. further teach, wherein the step of programming the two bits of parity data to the at least one parity memory block includes programming the two bits of parity data in a programming operation that includes three programming pulses and no verify operations (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158).
Regarding claim 4, Alrod et al. further teach wherein the user data includes at least fifteen programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165).
Regarding claim 5, Alrod et al. further teach, wherein the foggy data includes at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154).
Regarding claim 6, Alrod et al. further teach, wherein the step of programming the foggy data into the memory cells of the selected word line includes verify operations for a plurality of checkpoint data states that is fewer than the at least twelve data states and skipping verify operations for a plurality of non-checkpoint data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0166).
Regarding claim 7, Alrod et al. further teach, wherein the plurality of checkpoint data states includes four of the at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0157).
Regarding claim 8, Alrod et al. further teach, wherein the plurality of checkpoint data states includes three of the at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165).
Regarding independent claim 9, Alrod et al. teach a memory device, comprising: a plane including a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184 where memory array includes block BLK_0…7 and wordline WL); programming circuitry that is configured to: in a selected memory block of the plurality of memory blocks, program foggy data into the memory cells of a selected word line of the plurality of word lines in a first programming pass; in at least one parity memory block of the plurality of memory blocks, program two bits of parity data (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2006, 2401); read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct user data (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2008, 2405, 2409); and perform a second programming pass on the selected word line of the selected memory block (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2012, 2421).
Even though Alrod et al. teach programming / storing parity data bit but silent exclusively about program two bits of parity data. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Alrod et al. where two bits (0/1) data were generated and store / program in SLC memory (see specially Fig. 12, 16) in order to improve programming performance for the memory device (see paragraph 0006, 0178).
Regarding claim 10, Alrod et al. further teach, wherein the parity data is stored by the programming circuitry in a two-bits per memory cell storage format (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0157).
Regarding claim 11, Alrod et al. further teach, wherein when the programming circuitry programs the two bits of parity data to the at least one parity memory block, the programming circuitry performs a programming operation that includes three programming pulses and no verify operations (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154).
Regarding claim 12, Alrod et al. further teach, wherein the user data includes at least fifteen programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0157).
Regarding claim 13, Alrod et al. further teach, wherein the foggy data includes at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0171).
Regarding claim 14, Alrod et al. further teach, wherein during programming of the foggy data into the memory cells of the selected word line, the programming circuitry performs verify operations for a plurality of checkpoint data states that is fewer than the at least twelve data states and skipping verify operations for a plurality of non-checkpoint data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0166).
Regarding claim 15, Alrod et al. further teach, wherein the plurality of checkpoint data states includes no greater than four of the at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158).
Regarding claim 16, Alrod et al. further teach, wherein the plurality of checkpoint data states includes no greater than three of the at least twelve programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154).
Regarding independent claim 17, Alrod et al. teach an apparatus, comprising: a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184 where memory array includes block BLK_0…7 and wordline WL); a programming means for programming user data into the memory cells of a selected word line in a selected memory block, the programming means being configured to: in the selected memory block, program foggy data into the selected word line of in a foggy programming pass; in at least one parity memory block of the plurality of memory blocks, program two bits of parity data (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2006, 2401); read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct the user data (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2008, 2405, 2409); and perform a second programming pass on the selected word line of the selected memory block (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0181, 0184, step 2012, 2421).
Even though Alrod et al. teach programming / storing parity data bit but silent exclusively about program two bits of parity data. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Alrod et al. where two bits (0/1) data were generated and store / program in SLC memory (see specially Fig. 12, 16) in order to improve programming performance for the memory device (see paragraph 0006, 0178).
Regarding claim 18, Alrod et al. further teach, wherein the parity data is stored by the programming circuitry in a two-bits per memory cell storage format (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158).
Regarding claim 19, Alrod et al. further teach, wherein when the programming means programs the two bits of parity data to the at least one parity memory block, the programming means performs a programming operation that includes three programming pulses and no verify operations (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0166).
Regarding claim 20, Alrod et al. further teach, wherein the user data includes at least fifteen programmed data states (see Fig. 2-4, 7-13, 16-25, paragraph 0046-0048, 0077, 0086, 0125-0147, 0149-0154, 0156-0158, 0165-0172).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
Prosecution Insights