DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 70/30/202 have been fully considered but they are not persuasive. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-20 of U.S. Patent No. 12,204,364. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
18/979,763
US 12,204,364
Claim 13:
A method comprising: performing phase error correction, by a phase error corrector, to generate N clock output signals by using a feedback signal received by the phase error corrector; and adjusting the feedback signal in a first direction if a phase difference between a first clock output signal and a second clock output signal that are consecutive is less than 360/N degrees and adjusting the feedback signal in a second direction if greater than 360/N degrees.
Claim 13:
A method comprising: performing phase error correction, by a phase error corrector, based on N intermediate signals to generate N clock output signals, wherein performing the phase error correction reduces phase errors among the clock output signals using a feedback signal received by the phase error corrector; and adjusting the feedback signal in a first direction if a phase difference between a first clock output signal and a second clock output signal is less than 360/N degrees and adjusting the feedback signal in a second direction if greater than 360/N degrees.
Claim 14:
The method of claim 13, further comprising generating the feedback signal by cycling through N modes of phase detection operation and each mode of phase detection operation detects a phase error between two of the clock output signals and updates the feedback signal based on the detected phase error.
Claim 14:
The method of claim 13, further comprising generating the feedback signal by cycling through N modes of phase detection operation and each mode of phase detection operation detects a phase error between two of the clock output signals and updates the feedback signal based on the detected phase error.
Claim 15:
The method of claim 14, wherein a first mode compares a phase of a first clock output signal to a phase of a second clock output signal and adjusts the feedback signal in a first direction if a phase difference between the first clock output signal and the second clock output signal is less than 360/N degrees and adjusts the feedback signal in a second direction if greater than 360/N degrees.
Claim 15:
The method of claim 14, wherein a first mode compares a phase of a first clock output signal to a phase of a second clock output signal and adjusts the feedback signal in a first direction if a phase difference between the first clock output signal and the second clock output signal is less than 360/N degrees and adjusts the feedback signal in a second direction if greater than 360/N degrees.
Claim 16:
A quadrature clock generator comprising: a phase error corrector configured to generate four clock output signals and to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal; and a multiplexer configured to select and output two of the clock output signals based upon a current mode.
Claim 17:
The quadrature clock generator of claim 16, wherein the four clock output signals are generated from four intermediate signals, and a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 90 degrees, wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals and a first source/drain terminal configured to output one of the clock output signals.
Claim 16:
A quadrature clock generator comprising: a phase error corrector configured to receive four intermediate signals and to generate four clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 90 degrees and the phase error corrector is further configured to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal; and a multiplexer configured to select two of the clock output signals based upon a current mode.
Claim 17:
The quadrature clock generator of claim 16, wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals and a first source/drain terminal configured to output one of the clock output signals.
Claim 18:
The quadrature clock generator of claim 17, wherein the phase error corrector further includes a digital-to-analog converter configured to convert the feedback signal into a control voltage that is used to tune a pull down strength of the phase corrector transistor.
Claim 18:
The quadrature clock generator of claim 17, wherein the phase error corrector further includes a digital-to-analog converter configured to convert the feedback signal into a control voltage that is used to tune a pull down strength of the phase corrector transistor.
Claim 19:
The quadrature clock generator of claim 18, wherein the phase error corrector further includes a comparison transistor having a first source/drain terminal connected to a second source/drain terminal of the phase corrector transistor, a second source/drain terminal connected to an electrical ground, and a gate terminal configured to receive the control voltage.
Claim 19:
The quadrature clock generator of claim 18, wherein the phase error corrector further includes a comparison transistor having a first source/drain terminal connected to a second source/drain terminal of the phase corrector transistor, a second source/drain terminal connected to an electrical ground, and a gate terminal configured to receive the control voltage.
Claim 20:
The quadrature clock generator of claim 16, further comprising a phase error detector including: the multiplexer; an XOR gate configured to process the two selected clock output signals; a low pass filter configured to receive an output of the XOR gate; a slicer configured to process an output of the low pass filter; and a finite state machine configured to receive an output of the slicer and to adjust the feedback signal based on the received output of the slicer.
Claim 20:
The quadrature clock generator of claim 16, further comprising a phase error detector including: the multiplexer; an XOR gate configured to process the two selected clock output signals; a low pass filter configured to receive an output of the XOR gate; a slicer configured to process an output of the low pass filter; and a finite state machine configured to receive an output of the slicer and to adjust the feedback signal based on the received output of the slicer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 6,768,364).
In regard to Claim 16:
Wang discloses, in Figure 7, a quadrature clock generator comprising:
a phase error corrector (200) configured to generate four clock output signals (200 outputs) and to receive a feedback signal (Vcon[1:4]) and to reduce phase errors among the clock output signals based on the feedback signal (Column 8: lines 66-67 and Column 9: lines 1-7); and
a multiplexer (730) configured to select and output (730 outputs) two of the clock output signals (200 outputs) based upon a current mode (780 output, Column 9: lines 8-34).
Claim(s) 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (US 2009/0168552).
In regard to Claim 13:
Yoon discloses, in Figure 2, a method comprising: performing phase error correction, by a phase error corrector (290), to generate N clock output signals (ICLK_0, IBCLK_0, QCLK_0, QBCLK_0) by using a feedback signal (ICLK_0, IBCLK_0 are fed back to 220 and QCLK_0, QBCLK_0 are fed back to 240) received by the phase error corrector (290); and adjusting the feedback signal in a first direction if a phase difference between a first clock output signal (ICLK_0) and a second clock output signal (IBCLK_0) that are consecutive (¶ 0036: ICLK and IBCLK are consecutive outputs) is less than 360/N degrees (¶ 0036, where the phase detector 260 determines whether the phase difference between the clocks ICLK_O and QCLK_O or the clocks IBCLK_O and QBCLK_O is 90 degrees by detecting whether the two mixed signals have a phase difference of 180 degrees with each other and the phase corrector 290 controls phase delay times for the first and third input clocks ICLK and QCLK to output the first and third corrected clocks, i.e., the first and third clocks ICLK_O and QCLK_O, having a phase difference of 90 degrees therebetween) and adjusting the feedback signal in a second direction if greater than 360/N degrees (¶ 0035, where the first and second clocks ICLK_O and IBCLK_O have a phase difference of 180 degrees, and the third and fourth clocks QCLK_O and QBCLK_O have a phase difference of 180 degrees and the operation result is fed back to repeat the operation until the phase difference between the first and second clocks ICLK_O and IBCLK_O becomes exactly 180 degrees).
In regard to Claim 14:
Yoon discloses, in Figure 2, the method of claim 13, further comprising generating the feedback signal (ICLK_0, IBCLK_0 are fed back to 220 and QCLK_0, QBCLK_0 are fed back to 240) by cycling through N modes of phase detection operation (¶ 0041) and each mode of phase detection operation detects a phase error between two of the clock output signals (ICLK_0, IBCLK_0 and QCLK_0, QBCLK_0) and updates the feedback signal based on the detected phase error (280 receives the outputs of 220, 240 and outputs QPCCODE, QCODE, ICODE; Paragraphs 0030, 0036: lines 22-29; Paragraphs 0028-0030).
In regard to Claim 15:
Yoon discloses, in Figure 2, the method of claim 14, wherein a first mode compares a phase of a first clock output signal (ICLK_0) to a phase of a second clock output signal (IBCLK_0) and adjusts the feedback signal (ICLK_0, IBCLK_0 are fed back to 220 and QCLK_0, QBCLK_0 are fed back to 240) in a first direction if a phase difference between the first clock output signal (ICLK_0) and the second clock output signal (IBCLK_0) is less than 360/N degrees (¶ 0036: where the phase detector 260 determines whether the phase difference between the clocks ICLK_O and QCLK_O or the clocks IBCLK_O and QBCLK_O is 90 degrees by detecting whether the two mixed signals have a phase difference of 180 degrees with each other and the phase corrector 290 controls phase delay times for the first and third input clocks ICLK and QCLK to output the first and third corrected clocks, i.e., the first and third clocks ICLK_O and QCLK_O, having a phase difference of 90 degrees therebetween) and adjusts the feedback signal in a second direction if greater than 360/N degrees (¶ 0035, where the first and second clocks ICLK_O and IBCLK_O have a phase difference of 180 degrees, and the third and fourth clocks QCLK_O and QBCLK_O have a phase difference of 180 degrees and the operation result is fed back to repeat the operation until the phase difference between the first and second clocks ICLK_O and IBCLK_O becomes exactly 180 degrees).
Allowable Subject Matter
Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 17:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals and a first source/drain terminal configured to output one of the clock output signals.
In regard to Claim 20:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a phase error detector including: the multiplexer; an XOR gate configured to process the two selected clock output signals; a low pass filter configured to receive an output of the XOR gate; a slicer configured to process an output of the low pass filter; and a finite state machine configured to receive an output of the slicer and to adjust the feedback signal based on the received output of the slicer.
Claims 1-12 are allowed.
In regard to Claim 1:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the phase error corrector includes a plurality of phase corrector transistors, at least one of the plurality of phase corrector transistors having a gate terminal configured to receive a corresponding one of the intermediate signals, and at least one of the N output nodes is connected to terminals of two of the phase corrector transistors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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