DETAILED ACTION
This non-final action is responsive to communications: application field on 12/13/2024.
Claims 1-20 are pending. Claims 1, 15 and 20 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 12/13/2024. This IDS has been considered.
Specification Objections
6. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation
7. Claim language of claims 1, 15, and 20 broadly capture device structure and layout and the language is interpreted broadly. For example, any electrode or any 3D structure with width, length, height which “extend” in a particular direction can encompass extension in any one of the directions of width, length, or height. Similarly, arrangement or similar structural language can encompass multiple directions. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-3, 5-6, and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda-6298 et al. (US 2021/0066298 A1).
Regarding independent claim 1, Karda-6298 teaches a semiconductor device (Fig. 1: 100 “memory device”. See Fig. 1-Fig. 8 for illustrated components and functionality), comprising:
a cell region (Fig. 2: 201. See Fig. 6: 600) in which a plurality of unit structures (Fig. 6-Fig. 8: 3D cells and arrangement in Fig. 2 array) are arranged in a first direction (Fig. 6-Fig. 8: z-direction), perpendicular to an upper surface of a substrate (Fig. 6: 699 substrate), and a second direction (Fig. 6-Fig. 8: x-direction) and a third direction (Fig. 6-Fig. 8: y-direction), parallel to the upper surface of the substrate and intersecting each other; and
PNG
media_image1.png
665
1057
media_image1.png
Greyscale
a peripheral circuit region including circuits (Fig. 1: non array circuitry) configured for controlling the plurality of unit structures in the cell region (Fig. 1: control and biasing circuitry of array),
wherein each of the plurality of unit structures (Fig. 8) includes:
a first gate electrode layer (Fig. 8: WL1 741B) and a second gate electrode layer (Fig. 8: WL1 741T) separated from each other in the first direction (Fig. 8: z-direction) and extending in the second direction (Fig. 8: x-direction);
a first semiconductor layer (Fig. 8: 710 “channel” of T1) and a second semiconductor layer (Fig. 8: 720 “channel” of T2) separated from each other in the first direction (Fig. 8: z-direction) and between the first gate electrode layer and the second gate electrode layer (Fig. 8: WL1 741B, 741T) in the first direction (Fig. 8: z-direction), and extending in the third direction (see extension of 710, 720 in y-direction);
a plurality of insulating layers (Fig. 8: 718 “dielectric” segments. Alternately, see 717, 718, 719 in general congregation of dielectrics) between the first gate electrode layer (Fig. 8: WL1 741B) the second gate electrode layer (Fig. 8: WL1 741T), the first semiconductor layer (Fig. 8: 710) and the second semiconductor layer (Fig. 8: 710) in the first direction (Fig. 8: z-direction); and
a bit line electrode layer extending in the first direction (see Fig. 2: BL1 extends in z-direction) and electrically connected to the first semiconductor layer (Fig. 8: 710) and the second semiconductor layer (Fig. 8: 720) in the third direction (Fig. 8: y-direction).
Regarding claim 2, Karda-6298 teaches the semiconductor device of claim 1, wherein the peripheral circuit region includes:
a row decoder (Fig. 1: 108 “x-decoder”) electrically connected to the first gate electrode layer (WL1 741B) and the second gate electrode layer (WL1 741T) of each of the plurality of unit structures through a plurality of word lines (Fig. 1, Fig. 2: word lines. See para [0013]); and
a sense amplifier circuit (Fig. 1: 103 “sensing circuitry”) electrically connected to the bit line electrode layer (Fig. 1 and Fig. 6) of each of the plurality of unit structures through a plurality of bit lines (Fig. 1 and Fig. 6), and
wherein the first gate electrode layer and the second gate electrode layer included in one of the plurality of unit structures are commonly connected to one of the plurality of word lines (Fig. 2: gate of T1 and gate of T2 are commonly connected to WL1).
Regarding claim 3, Karda-6298 teaches the semiconductor device of claim 1, wherein the first gate electrode layer and the second gate electrode layer are offset from one another in the third direction (See Fig. 2 schematic where they are offset in x-direction and layout would follow substantially similar pattern).
Regarding claim 5, Karda-6298 teaches the semiconductor device of claim 1, wherein the plurality of insulating layers include:
a first insulating layer (Fig. 8: 719) between the first semiconductor layer (Fig. 8: 710) and the first gate electrode layer (Fig. 8: WL1 741B) in the first direction (Fig. 8: z-direction);
a second insulating layer (Fig. 8: 717) between the second semiconductor layer (Fig. 8: 720) and the second gate electrode layer (Fig. 8: WL1 741T) in the first direction (Fig. 8: z-direction); and
a third insulating layer (Fig. 8: 718) between the first semiconductor layer (Fig. 8: 710) and the second semiconductor layer (Fig. 8: 720) in the first direction (Fig. 8: z-direction).
Regarding claim 6, Karda-6298 teaches the semiconductor device of claim 5, wherein the third insulating layer includes a different material from the first insulating layer and the second insulating layer (para [0084]).
Regarding claim 11, Karda-6298 teaches the semiconductor device of claim 1, further comprising: a first transistor comprising at least a portion of the first gate electrode layer and the first semiconductor layer (See Fig. 8: T1 and electrode connections);
and a second transistor comprising at least a portion of the second gate electrode layer and the second semiconductor layer (See Fig. 8: T2 and electrode connections).
Regarding claim 12, Karda-6298 teaches the semiconductor device of claim 11, wherein a first threshold voltage of the first transistor is different from a second threshold voltage of the second transistor (see para [0102]: T2 is NFET and T1 is PFET)
Regarding claim 13, Karda-6298 teaches the semiconductor device of claim 12, wherein the first threshold voltage is a positive voltage and the second threshold voltage is a negative voltage (para [0102]).
11. Claims 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda-8112 et al. (US 2022/0278112 A1).
Regarding independent claim 15, Karda-8112 teaches a semiconductor device (Fig. 1: 100 “memory device”. See Fig. 1-Fig. 12C for illustrated components and functionality), comprising:
PNG
media_image2.png
708
775
media_image2.png
Greyscale
a cell region (Fig. 1: 101. See Fig. 2) including a plurality of memory cells (Fig. 2: 210…215 “memory cells”) electrically connected to a plurality of word lines (Fig. 2: WL1…WLn) and a plurality of bit lines (Fig. 2: BL1…BL2. See para [0024]); and
a peripheral circuit region (Fig. 1: non array circuitry) including circuits configured for controlling the plurality of memory cells through the plurality of word lines and the plurality of bit lines (Fig. 1, Fig. 2 in context of para [0013], para [0016]),
wherein each of the plurality of memory cells (Fig. 2: 210) includes a first transistor and a second transistor (para [0025], Fig. 2: T1, T2), and
the first transistor (Fig. 2: T1) includes a first gate (Fig. 2: T1 transistor channel region) and first active regions (Fig. 2: T1 right D/S terminal), and the second transistor (Fig. 2: T2) includes a second gate (Fig. 2: T1 transistor channel region) and second active regions (Fig. 2: T2 right D/S terminal), and
in each of the plurality of memory cells (see Fig. 2: 210, Fig. 5A, Fig. 5B), the first gate and the second gate are commonly connected to one of the plurality of word lines (Fig. 2: WL1 is commonly connected to T1, T2. See also Fig. 5A, Fig. 5B),
a first one of the first active regions (Fig. 2: T1 right D/S terminal) and a first one of the second active regions (Fig. 2: T2 right D/S terminal) are commonly connected to one of the plurality of bit lines (Fig. 2: BL1),
a second one of the first active regions (Fig. 2: T1 left D/S terminal) is connected to a ground node supplying a ground voltage (Fig. 2: 297 gnd connection), and
a second one of the second active regions (Fig. 2: T2 left D/S terminal which is 202 “charge storage structure”) is configured as a storage node in which a charge representing a logic state of the memory cell is stored (para [0077]).
Regarding claim 16, Karda-8112 teaches the semiconductor device of claim 15, wherein the peripheral circuit region includes: a row decoder (Fig. 1: 108 “x-decoder”) electrically connected to the plurality of memory cells through the plurality of word lines (Fig1: connected to WLs in 101); and a sense amplifier circuit (Fig. 1: 103 “sensing circuitry”) electrically connected to the plurality of memory cells (Fig. 1: 101) through the plurality of bit lines (Fig. 1, Fig. 2 in context of para [0016]-para [0017], para [0021], para [0025].
Regarding claim 17, Karda-8112 teaches the semiconductor device of claim 16, wherein during a read operation for a selected memory cell among the plurality of memory cells, the row decoder is configured to provide a first turn-on voltage to a select word line connected to the selected memory cell to turn on the first transistor (see Fig. 2 in context of para [0032], para [0040], para [0041], para [0043]).
Regarding claim 18, Karda-8112 teaches the semiconductor device of claim 16, wherein during a write operation for a selected memory cell among the plurality of memory cells, the row decoder is configured to provide a predetermined write bias voltage to a select bit line connected to the select memory cell, and inputs a second turn-on voltage to a select word line connected to the selected memory cell to turn on the second transistor (see Fig. 2 in context of para [0032], para [0040], para [0041], para [0043]).
Regarding independent claim 20, Karda-8112 teaches a semiconductor device (Fig. 1: 100 “memory device”. See Fig. 1-Fig. 12C for illustrated components and functionality), comprising:
a plurality of memory cells (Fig. 2: 210…215 “memory cells”) connected to a plurality of word lines (Fig. 2: WL1…WLn) and a plurality of bit lines (Fig. 2: BL1…BL2. See para [0024]);
a row decoder (Fig. 1: 108 “x-decoder”) configured to control voltages on each of the plurality of word lines (Fig. 1: 108 in context of para [0016], para [0017]); and
a sense amplifier circuit (Fig. 1: 103 “sensing circuitry”) configured to control voltages on each of the plurality of bit lines (Fig. 1: 103 in context of para [0021]),
wherein each of the plurality of memory cells (Fig. 2: 210) includes a pair of transistors (para [0025], Fig. 2: T1-T2),
the row decoder (Fig. 1: 108 coupled to WL’s) is configured to provide a common control voltage (para [0030]: “word line signals” WL1) to the pair of transistors included in a selected memory cell (Fig. 2: T1-T2) among the plurality of memory cells, through one select word line (Fig. 2: WL1) of the plurality of word lines (para [0030]), and
a first transistor of the pair of transistors is turned on and a second transistor of the pair of transistors is turned off by the common control voltage (Fig. 2 in context of para [0025]: “…transistor T1 can be a p-channel FET (PFET), and transistor T2 can be an n-channel FET (NFET)…”. Thus when “high” is applied on WL1, NFET T2 is on but PFET T1 is off).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Koya (US 2019/0066762 A1): Fig. 1-Fig. 6 disclosure applicable for all claims.
Karda (US 2024/0074211 A1): Fig. 1-Fig. 9C applicable for all claims.
Sato et al. (US 2023/0084611 A1): Sato teaches a semiconductor device (Fig. 3: 300 and Fig. 2: 200 memory) comprising: a write transistor (see Fig. 2: 210, Fig. 3: 210) and a read transistor (see Fig. 2: 220, Fig. 3: 220) disposed over a substrate (Fig. 3: 102 substrate/ support structure); the write transistor (Fig. 3: 210 bottom transistor) comprises a write word line (Fig. 3: 214 WWL) disposed on a plane that is substantially parallel to a surface of the substrate over the substrate (Fig. 3: see plane parallel to surface of 102); a write gate dielectric layer (Fig. 3, Fig. 4A in context of para [0055]: “gate dielectric material” between channel 310 and gate stack 312) disposed over the write word line (Fig. 3: 214 WWL); a write channel layer (Fig. 3: 310 “channel layer”) disposed over the write gate dielectric layer (Fig. 3, Fig. 4A in context of para [0055]: “gate dielectric material” between channel 310 and gate stack 312); and a write bit line (Fig. 3: 212 WBL) disposed over the substrate (Fig. 3: 102) and extending in a direction substantially perpendicular to the surface of the substrate, and electrically connected to one end of the write channel layer (See Fig. 2 and Fig. 3: coupled to first end of 310), and the read transistor (Fig. 3: 220 top transistor) comprises a read channel layer (Fig. 3: 320 “channel layer”) disposed on the plane over the substrate (Fig. 3: see plane parallel to surface of 102); a read gate dielectric layer (Fig. 4A in context of para [0055]: “gate dielectric material” between channel 320 and gate stack 322-2) disposed over the read channel layer (Fig. 3: 320); and a read gate electrode layer (Fig. 3: 322-2 “gate stack”) disposed over the read gate dielectric layer (Fig. 3, Fig. 4A in context of para [0055]: “gate dielectric material” between channel 320 and gate stack 322-2) and electrically connected to the other end of the write channel layer (See Fig. 2 and Fig. 3: coupled to second end of 310).
Allowable Subject Matter
Claims 4, 7-10, 14, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
Prosecution Insights