Prosecution Insights
Last updated: October 23, 2026
Application No. 18/980,363

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND CLEANING METHOD

Final Rejection §103
Filed
Dec 13, 2024
Priority
Oct 31, 2022 — JP 2022-174530 +1 more
Examiner
BERGNER, ERIN FLANAGAN
Art Unit
1713
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Tokyo Electron Limited
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
508 granted / 665 resolved
+11.4% vs TC avg
Strong +31% interview lift
Without
With
+30.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
701
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
22.5%
-17.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 665 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-18 and 21-22 are pending Claims 6-7 and 17 have been amended Claims 19-20 have been canceled Claims 21-22 are new Claim Interpretation The term “circuitry” is claims 1-19 is being interpreted based on the definition provided in para 22 of the filed specification as “In the disclosure, the circuitry, units, or means are hardware that carry out or are programmed to perform the recited functionality”, “The functionality of the elements disclosed herein may be implemented using circuitry or processing circuitry which includes general purpose processors, special purpose processors, integrated circuits, ASICs (“Application Specific Integrated Circuits”), FPGAs (“Field-Programmable Gate Arrays”), conventional circuitry and/or combinations thereof which are programmed, using one or more programs stored in one or more memories, or otherwise configured to perform the disclosed functionality. Processors and controllers are considered processing circuitry or circuitry as they include transistors and other circuitry therein.” Allowable Subject Matter Claims 1-16 are allowed. The following is a statement of reasons for the indication of allowable subject matter: as discussed below. The prior art teaches a plasma processing apparatus including an edge ring that is lifted during cleaning after a selected number of wafers are processed including cleaning with the gases recited in claim 1. Hayshi 2021/0098238 teaches a two-part edge ring including a lift mechanism which passes through one ring and lifts a second ring (see fig. 3-9, para. 50-79). The combination of Koshimizu US 2021/0272782 (US’782) in view of Goto et al. US 2014/0187053 (US’053) and Hayshi 2021/0098238 do not teach a first ring mounting surface, and a second ring mounting surface; a first ring disposed to surround a substrate on the substrate mounting surface and including an inner annular portion and an outer annular portion, the inner annular portion of the first ring being mounted on the first ring mounting surface; a second ring including an inner annular portion and an outer annular portion, the inner annular portion of the second ring being configured to support the outer annular portion of the first ring, the outer annular portion of the second ring being mounted on the second ring mounting surface or circuitry configured to perform the particular combination of cleaning steps using the recited cleaning gases and use of a cleaning substate recited in claim 1 steps a)-h), as in the context of claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 17-18 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Koshimizu US 2021/0272782 (US’782) in view of Goto et al. US 2014/0187053 (US’053). Regarding claim 17, US’782 teaches a substrate processing apparatus (abstract, plasma processing apparatus) comprising: a plasma processing chamber (chamber 10, para. 30-31, fig. 2); a stage disposed in the plasma processing chamber and having a substrate mounting surface and a ring mounting surface an edge ring mounted on the ring mounting surface to surround a substrate on the substrate mounting surface (substrate support 11 including substrate mounting surface/electro static chuck 112, edge ring 113 and edge ring placement surface 11b, para. 30-32, see fig. 2); a lifter configured to lift and lower the edge ring with respect to the ring mounting surface with a plurality of lifter pins (lift pins 51b are raised and lowered by actuators 52b, para. 42-44, see fig. 2 and 4); and circuitry (the controller 1b processes computer-executable instructions to cause the plasma processing apparatus 1a to perform various processes, para. 45, fig. 2), wherein the circuitry is configured to: a) control the plasma processing apparatus to perform plasma processing of the substrate that is disposed on the substrate mounting surface (substrate etching is performed on a substrate in the chamber, para. 51-60, see fig. 2-3); b) perform the a) on a first number of substrates (the etching is completed on a predetermined number of substrates, para. 60, fig. 3); c) control the plurality of lifter pins to lift, after the b), the edge ring with respect to the ring mounting surface (the controller 1b controls the respective components of the plasma processing apparatus 1a and the transfer system 1000 to move the edge ring 113 disposed on the substrate support 11 to a first position spaced apart from the substrate support 11 (step S32), para. 47, see fig. 3); d) control the plasma processing apparatus to perform, in a state of the c), first cleaning in the plasma processing chamber with first plasma generated from a first cleaning gas (the controller 1b generates a local plasma between the edge ring 113 and the substrate support 11 (step S33) to clean the chamber, para. 49-54, see fig. 3-4); the first cleaning being performed with the substrate mounting surface exposed (first placement surface 11a remains exposed during the local plasma cleaning with lower plasma density suppressing damage to 11a, para. 54, see fig. 4), the first cleaning gas includes at least one selected from the group consisting of an O2 gas (The gas to be supplied may be, for example, a gas containing any one of oxygen (O2), para. 50), e) control the plasma processing apparatus to perform a) on a second number of substrates (the state of the chamber is returned to a before cleaning state, which would necessarily return the chamber to step S31 of processing a predetermined number of substrates, para. 47-53, see fig. 3); f) control the plurality of lifter pins to lift, after the e), the edge ring with respect to the ring mounting surface (the cleaning process is performed again after the second predetermined step of wafers, which would necessarily include lifting the edge ring to perform the second cleaning); and g) control the plasma processing apparatus to perform, in a state of the f), second cleaning in the plasma processing chamber with second plasma generated from a second cleaning gas (as discussed above plasma cleaning is performed to clean the chamber). US’782 does not teach the second number being larger than the first number, in a state of the f) and in a state where a cleaning substrate is placed on the substrate mounting surface, second cleaning in the plasma processing chamber with second plasma generated from a second cleaning gas, the second cleaning gas including a halogen-containing gas. US’053 teaches a method of cleaning a thin film forming apparatus (abstract). The cleaning process can be selected based on the number of wafers that have been processed and corresponding accumulation of debris within the chamber (para. 50 and 68). US’782 further teaches the determination of the timing for performing the cleaning in step S31 may be performed based on, for example, any one of the following determinations. (1) Whether the etching has been performed a predetermined number of times (2) Whether the etching has been completed on a predetermined number of substrates (3) Whether the cumulative time during which the etching has been performed reaches a predetermined time (4) Whether the amount of deposits calculated based on deposit distribution information 622 is equal to or higher than a threshold value (5) Whether the electrostatic adsorption operation of the substrate (wafer) or the edge ring is normal. Further, the determination of the timing for performing the cleaning may be performed based on the following determinations, in addition to the determinations described above (para. 58-64). Therefore, the combination of teaching of US’053 and US’782 includes embodiments where different metrics are used to determine when to perform cleaning and therefore a different number of substrates may be processed for each metric threshold and the number of substrates process between cleaning can motivate different cleaning conditions. and the second cleaning gas includes a halogen-containing gas. US’782 further teaches the gas to be supplied is a gas suitable for a cleaning process using a plasma processing, that is, the removal of deposits that adhere to the inside of the chamber 10. The gas to be supplied may be, for example, a gas containing any one of oxygen (O2), fluorine (F), nitrogen (N2), and hydrogen (H). The gas to be supplied may be, for example, NH3, NF3, or CF2. Accordingly, the cleaning gas includes a gas selected from the group consisting of oxygen-containing gas, NH3 gas, NF3 gas, CF2 gas, and a combination thereof (para. 50). In order to suppress the damage to the first placement surface 11a caused from the cleaning, the cleaning may be performed after a dummy wafer is placed on the first placement surface 11a (para. 56-57). Since US’053 teaches different metrics used to determine when to perform cleaning and therefore a different number of substrates may be processed for each metric threshold and the number of substrates process between cleaning can motivate different cleaning conditions, the cleaning gases and cleaning condition can be selected to be different for the first cleaning and the second cleaning out of the alternative cleaning conditions taught by US’782. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of US’782 to include the second number being larger than the first number, in a state of the f) and in a state where a cleaning substrate is placed on the substrate mounting surface, second cleaning in the plasma processing chamber with second plasma generated from a second cleaning gas, the second cleaning gas including a halogen-containing gas because the combination of teaching of US’053 and US’782 includes embodiments where different metrics are used to determine when to perform cleaning and therefore a different number of substrates may be processed for each metric threshold result in different cleaning conditions be selected from cleaning gasses that include halogen containing gases and the use of dummy substrates and it is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose the idea of combining them flows logically from their having been individually taught in the prior art, see MPEP 2144.06. Regarding claim 18, the modified apparatus of US’782 teaches the processing apparatus according to claim 17. The modified apparatus of US’782 further teaches wherein a condition for the second cleaning is different from a condition for the first cleaning (the combination of teaching of US’053 and US’782 includes embodiments where different metrics are used to determine when to perform cleaning and therefore a different number of substrates may be processed for each metric threshold and the number of substrates process between cleaning can motivate different cleaning conditions). Regarding claim 21, the modified apparatus of US’782 teaches the processing apparatus according to claim 17. The modified apparatus of US’782 further teaches wherein the cleaning substrate has an outer diameter smaller than an inner diameter of the edge ring (The inner diameter of the edge ring 113 is smaller than the outer diameter of an ordinary product wafer. Thus, the edge ring 113 may not be automatically lifted by the second lifter pin 51b in a state where the product wafer is placed on the first placement surface 11a. Thus, the outer diameter of the dummy wafer for the cleaning is set to be smaller than the inner diameter of the edge ring 113. When the outer diameter of the dummy wafer is set to be smaller than that of the product wafer, the edge ring 113 may be automatically moved up and down in a state where the dummy wafer is placed on the substrate support 11, para. 56). Regarding claim 22, the modified apparatus of US’782 teaches the processing apparatus according to claim 17. The modified apparatus of US’782 further teaches wherein the halogen-containing gas includes a CF-containing gas or an NF3 gas (as discussed above, the gas to be supplied may be, for example, NH3, NF3, or CF2). Response to Amendment Applicant’s amendments to independent claim 17 to include additional subject matter regarding the first and second cleaning processes has changed the scope of claim 17. However, upon further consideration, the teachings of US’782 and US’053 still appear to read on the claimed invention therefore a new ground(s) of rejection is made under 103 as obvious over US’782 in view of US’053 which includes both the rejection of claim 17 as stated in the non-final office action mailed 7-1026 and additional discussion regarding the teachings of US’782 and US’053 relating to the features added to claim 17. Applicants amendments to claims 6-7 have overcome the 112b rejection cited in the non-final office action, therefore the 112b rejection has been withdrawn. Response to Arguments Applicant's arguments filed 7-30-26 have been fully considered but they are not persuasive. Applicant arguments that in the statement of reasons for the indicated allowable subject matter, the Examiner explained that the cited art does not teach circuitry configured to perform the particular combination of cleaning steps using the recited cleaning gases and the use of a cleaning substrate, as recited in claim 1 and to place the apparatus claims in condition for allowance, Applicant has amended independent claim 17 to incorporate this same subject matter, has been considered but is not deemed persuasive. As discussed in the allowable subject matter section of the non-final office action, the reasons for allowance is the combination of all features recited in claim 1 including but not limited to a first ring mounting surface, and a second ring mounting surface; a first ring disposed to surround a substrate on the substrate mounting surface and including an inner annular portion and an outer annular portion, the inner annular portion of the first ring being mounted on the first ring mounting surface; a second ring including an inner annular portion and an outer annular portion, the inner annular portion of the second ring being configured to support the outer annular portion of the first ring, the outer annular portion of the second ring being mounted on the second ring mounting surface. Further, claim 1 circuitry requires cleaning steps including a particular combination of lifting the first ring in relation to the second ring having a particular arrangement of lift pins which are not required by the amendments made to claim 17. Additionally claim 1 requires a step “h) control the vacuum transfer apparatus to transfer the first ring from the plasma processing chamber to the ring stocker to replace the first ring”, which is not required by amended claim 17. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIN FLANAGAN BERGNER whose telephone number is (571)270-1133. The examiner can normally be reached M-F 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIN F BERGNER/Primary Examiner, Art Unit 1713
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Prosecution Timeline

Dec 13, 2024
Application Filed
Jul 10, 2026
Non-Final Rejection mailed — §103
Jul 30, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+30.8%)
2y 6m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 665 resolved cases by this examiner. Grant probability derived from career allowance rate.

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