DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1 and 20.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over YAMAOKA PG PUB 20190371407 (hereinafter YAMAOKA), in view of Chiang PG PUB 20190147956 (hereinafter Chiang).
Regarding independent claim 1, Yamaoka teaches a memory device (figures 1-3, [0028]) comprising:
a first block (BLK0 in figure 1) including a first memory string (string connected to ST1 in figure 2) having a first transistor (ST1 in figure 2) at an end;
a second transistor (TR10 in figure 3) having a first end connected to a gate of the first transistor (ST1 in figure 2);
a first interconnect (TG in figure 3) connected to a gate of the second transistor (TR10 in figure 3);
a block decoder (BD in figure 3) connected to one end of the first interconnect (TG in figure 3).
But Yamaoka does not teach a third transistor having a first end connected to the other end of the first interconnect; and a power supply connected to a second end of the third transistor.
However, Chiang teaches in figures 1-1 a level shifter includes transistor M1, having one terminal connected to node NC1 (VC1), which corresponds to the control node/interconnect from the decoder, while the other terminal is connected toward the supply (VDD1 in figure 1, [0015]-[0026]). Decoder 120 generates VC1/VC2 to control transistors M1 or M3.
Yamaoka and Chiang are analogous art because they address the same field of endeavor: memory block decoder control methods therefor. One of the ordinary skill would have understood that Chiang’s output transistor M1 replace the supply-side transistor driving the transfer -gate interconnect of Yamaoka while maintaining the same electrical function of supply the decoder output to the transfer-gate line. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Yamaoka and Chiang before him, to modify the block-decoder/transfer-gate driving circuit of Yamaoka to include the level shifting out stage implementation of Chiang, because employing Chiang’s level shifting output state would have provided a reliable supply-driven control signal capable of driving the long decoder interconnects used by Yamaoka while improving robustness of the decoder output stage.
Regarding claim 2, the combination of Yamaoka and Chiang teaches the memory device of claim 1, wherein: the block decoder (BD in figure 3 of Yamaoka) and the third transistor are aligned with the second transistor in a first direction on a substrate (Yamaoka teaches in figure 13, 15, the block decoder circuit, the transfer transistor/switch circuitry, and the transistor coupled to the supply are arranged along the same layout direction adjacent to memory blocks, see [0178]-[0186] of Yamaoka, which describe the layout of block decoder region, transfer gate region, and switch region); and the first interconnect has a main portion that connects the block decoder and the third transistor (Yamaoka teaches an interconnect extending between the block decoder (BD) and the switch circuitry through the transfer-gate region, see figure 13-16 and [0178]-[0186], where the interconnect layers electrically connect the block decoder to the switching circuitry), and the main portion includes a portion that passes above the second transistor in the first direction on the substrate (Yamaoka teaches in figure 13-15, the interconnect extends across (i.e., passed over in plan view) the transfer-gate/switch transistor region while connecting the decoder and supply circuitry).
Regarding claim 3, the combination of Yamaoka and Chiang teaches the memory device of claim 2, wherein the block decoder and the third transistor are located so as to sandwich the second transistor in the first direction (Yamaoka teaches in figures 15- 16 the switch region (SW) is disposed between the block decoder (BD) and the transfer-gate/interconnect region, thereby positioning the decoder and supply-side circuitry on opposite sides of the switch transistor along the first layout direction).
Regarding claim 4, the combination of Yamaoka and Chiang teaches the memory device of claim 3, wherein the block decoder and the third transistor are adjacent to the second transistor in the first direction (Yamaoka teaches in figures 15-16, and [0178]-[0186] block decoder region adjacent the switch region, while the switch region is adjacent the transfer circuitry).
Regarding claim 5, the combination of Yamaoka and Chiang teaches The memory device of claim 3, wherein: the block decoder is separated from the second transistor in a second direction intersecting with the first direction (Yamaoka teaches in figures 17-20 the block decoder region (BD) and switch circuitry are offset in the orthogonal layout direction, [0204]-[0236] of Yamaoka teaches the modified layout in which the decoder is separated from the switch circuitry in the perpendicular direction); and the main portion of the first interconnect further includes a portion extending in the second direction between the block decoder and the second transistor (Yamaoka teaches in figures 17-20 and [0221]-[0236] that interconnect is routed first in one layout direction and then extends in the orthogonal direction to electrically couple the decoder tot eh switch region).
Regarding claim 6, the combination of Yamaoka and Chiang teaches the memory device of claim 2, further comprising: a second block including a second memory string including a fourth transistor at an end (Yamaoka teaches in figure 2 multiple blocks (BLK0-BLKn), each including memory strings); and a fifth transistor having a first end connected to a gate of the fourth transistor and a gate connected to the first interconnect (Yamaoka teaches in figure 3, 13-16 each block includes corresponding transfer-gate transistors controlled by common interconnects), wherein: the second transistor and the fifth transistor are aligned in a second direction intersecting with the first direction on the substrate (Yamaoka in figures 13, 15 transfer-gate transistors arranged along the orthogonal direction for adjacent blocks); and the main portion of the first interconnect further includes a portion extending in the first direction so as to pass above the fifth transistor (Yamaoka teaches in figures 13-16 the same interconnect extending across multiple transfer-gate transistors).
Regarding claim 7, the combination of Yamaoka and Chiang teaches the memory device of claim 6, wherein: the block decoder is adjacent to the second transistor and the fifth transistor in the first direction; and the third transistor is separated from the second transistor and the fifth transistor in the first direction (figure 16 of Yamaoka).
Regarding claim 8, the combination of Yamaoka and Chiang teaches the memory device of claim 6, wherein: the block decoder is separated from the second transistor and the fifth transistor in the first direction; and the third transistor is adjacent to the second transistor and the fifth transistor in the first direction (Yamaoka modified layouts (figures 17-20) teaches relocating decoder/switch circuitry to different sides while preserving functionality).
Regarding claim 9, the combination of Yamaoka and Chiang teaches the memory device of claim 6, wherein the third transistor is located alongside the block decoder with respect to the second transistor and the fifth transistor in the first direction (figure 16 of Yamaoka teaches SW located alongside BD).
Regarding claim 10, the combination of Yamaoka and Chiang teaches the memory device of claim 1, wherein the block decoder includes: a sixth transistor (M5 in figure 2 of Chiang, [0023]-[0026] of Chiang) and a seventh transistor (M6 in figure 2 of Chiang) each having a first end connected to the one end of the first interconnect and having different conductivity types; an eighth transistor (M7 in figure 2 of Chiang) having a first end connected to a second end of the sixth transistor and a second end to which a first voltage is applied; and a ninth transistor (M8 in figure 2 of Chiang) having a first end connected to a second end of the seventh transistor, wherein the third transistor, the eighth transistor, and the ninth transistor each have a gate connected to a second interconnect (It would have been obvious to employ Chiang’s compact decoder inside Yamaoka’s block decoder because Chiang improved decoder reliability while reducing area).
Regarding claim 11, the combination of Yamaoka and Chiang teaches the memory device of claim 10, further comprising a tenth transistor (M9 or M10 in figure 2 of Chiang) provided between the other end of the first interconnect and the first end of the third transistor, wherein the sixth transistor, the seventh transistor, and the tenth transistor each have a gate connected to a third interconnect.
Regarding claim 12, the combination of Yamaoka and Chiang teaches the memory device of claim 10, further comprising an eleventh transistor (M10 in figure 2 of Chiang) having a first end connected to the other end of the first interconnect, a second end connected to the first end of the third transistor, and a gate connected to a fourth interconnect, wherein the block decoder includes a level shifter having an input terminal connected to a gate of the sixth transistor and a gate of the seventh transistor and an output terminal connected to the fourth interconnect (figure 2, [0023]-[0026] of Chiang).
Regarding claim 13, the combination of Yamaoka and Chiang teaches the memory device of claim 10, further comprising a control circuit connected to a second end of the ninth transistor via a fifth interconnect, wherein the control circuit is configured to determine whether the first interconnect is disconnected based on a voltage of the fifth interconnect (Yamaoka teaches in figures 4, 6-9, 17-18, [0080]-[0110] of Yamaoka).
Regarding claim 14, the combination of Yamaoka and Chiang teaches the memory device of claim 13, wherein in an operation in which the power supply applies a second voltage that is lower than the first voltage, the control circuit is configured to determine that the first interconnect is not disconnected if the voltage of the fifth interconnect decreases from the first voltage toward the second voltage (figures 6 -8 of Yamaoka teaches timing diagrams monitoring node voltage while changing supply voltages).
Regarding claim 15, the combination of Yamaoka and Chiang teaches the memory device of claim 13, wherein in an operation in which the power supply applies the first voltage, the control circuit is configured to determine that the first interconnect is not disconnected if the voltage of the fifth interconnect increases from a second voltage that is lower than the first voltage toward the first voltage (The same monitoring circuitry necessarily evaluates the node voltage during both decreasing and increasing supply transistor, performing the complementary operation of the same circuit would have been an obvious use of the same circuit).
Regarding claim 16, the combination of Yamaoka and Chiang teaches the memory device of claim 10, further comprising a pad connected to a second end of the ninth transistor via a fifth interconnect (Yamaoka teaches in figure 4, 6-9, [0080]-[0110] PAD monitoring circuitry).
Regarding claim 17, the combination of Yamaoka and Chiang teaches the memory device of claim 1, wherein: the first memory string further includes a memory cell transistor having a gate connected to a word line; and the first transistor (ST1 in figure 2 of Yamaoka) connects between the memory cell transistor and a bit line at the end of the first memory string (figure 2 of Yamaoka).
Regarding claim 18, the combination of Yamaoka and Chiang teaches the memory device of claim 17, further comprising a twelfth transistor (TR1 in figure 2, 3 of Yamaoka) having a gate connected to the first interconnect (TG in figure 2 of Yamaoka); the first memory string further includes a thirteenth transistor (ST2 in figure 2 of Yamaoka) having a gate connected to the twelfth transistor and connecting between the memory cell transistor and a source line at an end opposite to the first transistor.
Regarding claim 19, the combination of Yamaoka and Chiang teaches the memory device of claim 1, wherein the block decoder is configured to: turn off the second transistor via the first interconnect when the first block is selected; and turn on the second transistor via the first interconnect when the first block is not selected (Yamaoka teaches in figure 6-8, [0061]-[0077], [0080]-[0110], decoder output BLKSEL/BLKSELn control the transfer gate line to disable the switch transfer in the selected block and enable corresponding transistors in non-selected blocks).
Regarding independent claim 20, claim 20 is substantially identical to claim 1 with the additional functional languish of claim 19 regarding applying a voltage tot eh first interconnect and turning the second transistor OFF/ON depending on block selection.
Yamaoka teaches overall memory architecture, block decoder, transfer-gate control, routing and operation, while Chaing is relied on for teaching specific decoder/level shifter transistor implementation. The combination of Yamaoka and Chiang renders obvious every limitation.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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