CTNF 18/980,921 CTNF 85772 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending in the application. Information Disclosure Statement The information Disclosure Statement (IDS) Form PTO-1449, filed 12/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner. Drawings The drawings submitted on 12/13/2024. These drawings are review and accepted by the examiner. 07-30-03-h AIA Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are: Apparatus claims 1-13’s “a control means” that is “configured to” perform recited operations; Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof. If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Penzo et al (US 2022/0406380 A1 hereinafter “Penzo”) in view of Takekida (US 11,386,959 B2 hereinafter “Takekida”) . Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Regarding Independent Claim 1 , Penzo, for example in Figs. 1-13, discloses a memory apparatus (see for example in Figs. 1-2 related in Figs. 3-13), comprising: memory cells (e.g., memory cells; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) each connected to one of a plurality of word lines (e.g., word lines; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) and disposed in memory holes (see for example in Figs. 3-4 related in Figs. 1-2, 5-13) extending vertically through a stack of the plurality of word lines (see for example in Figs. 3-4 related in Figs. 1-2, 5-13), the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., data states; in Figs. 5-7 related in Figs. 1-4, 8-13), the memory cells form a block including a first sub-block (e.g., lower set of word lines; in Fig. 4C related in Figs. 1-3, 5-13) vertically below a second sub-block (e.g., upper set of word lines; in Figs. 4C related in Figs. 1-3, 5-13) to define an interface region therebetween (e.g., joint area; in Fig. 4C related in Figs.1-3, 5-13), the plurality of word lines including a plurality of dummy word lines being disposed adjacent the interface region (e.g., WLDU and WLDL; in Fig. 4C related in Figs. 1-3, 5-13); and a control (e.g., controller 204; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13) means configured to: erase the memory cells in one of the first sub-block and the second sub-block individually in an erase operation (see paragraph [0082+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13), and read the threshold voltage of the memory cells connected to one or more of the plurality of dummy word lines (see paragraph [0090+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13) and adjust based on the threshold voltage of the memory cells connected to one or more of the plurality of dummy word lines (see for example in Figs. 1-7 related in Figs. 8-13) relative to which of the one of the first sub-block and the second sub-block is erased in the erase operation (see for example in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13). However, Penzo is silent with regard to adjust based on at least one dummy target voltage . In the same field of endeavor, Takekida, for example in Figs. 1-7, discloses to adjust based on at least one dummy target voltage (e.g., to adjust selected WL/WLD and unselected WL/WLD voltage; in Figs. 5-7 related in Figs. 1-4). It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Penzo such as word line zoned adaptive initial program voltage for non-volatile memory (see for example in Figs. 1-13 of Penzo) by incorporating the teaching of Takekida such as semiconductor storage device (see for example in Figs. 1-7 of Takekida), for the purpose of controlling the sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string (Takekida, see abstract). The structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 2 , the above Penzo/Takekida, combination discloses wherein each of the memory holes define a channel and the control means is further configured to apply a plurality of erase voltage pulses of an erase voltage to the channel of the memory holes including the memory cells (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) being erased in the erase operation each followed by an erase verify pulse of an erase verify voltage applied to ones of the plurality of word lines connected to the memory cells being erased to verify the memory cells are erased in an erase verify of the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 3 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage is selected to increase potential of the channel for a selected one of the first sub-block and the second sub-block during a program operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the memory cells of the selected one of the first sub-block and the second sub-block being programmed during the program operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 4 , the above Penzo/Takekida, combination discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) and at least one source-side select gate transistor on a source-side of each of the memory holes, the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the plurality of dummy word lines includes an upper dummy word line and a lower dummy word line disposed vertically below the upper dummy word line, and the control means (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) is further configured to: read the threshold voltage of the memory cells connected to the upper dummy word line using a predetermined dummy read level and adjust based on the threshold voltage of the memory cells connected to the upper dummy word line relative to the predetermined dummy read level in response to the first sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and read the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and adjust based on the threshold voltage of the memory cells connected to the lower dummy word line relative to the predetermined dummy read level in response to the second sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 5 , the above Penzo/Takekida, combination discloses wherein the control means is further configured to: adjust the threshold voltage of the memory cells connected to the lower dummy word line (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) in response to the first sub-block being erased in the erase operation; and adjust the threshold voltage of the memory cells connected to the upper dummy word line in response to the second sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 6 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the control means (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) is further configured to: begin erasing the memory cells in the second sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); finish erasing the memory cells in the second sub-block in the erase operation; read the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and count a lower dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determine whether the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 7 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the control means (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) is further configured to: begin erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); finish erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); read the threshold voltage of the memory cells connected to the upper dummy word line using the predetermined dummy read level and count an upper dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determine whether the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); program the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding Independent Claim 8 , Penzo, for example in Figs. 1-13, discloses a controller (e.g., controller 104; in Figs.1-2 related in Figs.3-13) in communication with a memory apparatus (e.g., memory 200; in Figs. 1-2 related in Figs. 3-13) including memory cells (e.g., memory cells; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) each connected to one of a plurality of word lines (e.g., word lines; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) and disposed in memory holes (see for example in Figs. 3-4 related in Figs. 1-2, 5-13) extending vertically through a stack of the plurality of word lines (see for example in Figs. 3-4 related in Figs. 1-2, 5-13), the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., data states; in Figs. 5-7 related in Figs. 1-4, 8-13), the memory cells form a block including a first sub-block (e.g., lower set of word lines; in Fig. 4C related in Figs. 1-3, 5-13) vertically below a second sub-block (e.g., upper set of word lines; in Figs. 4C related in Figs. 1-3, 5-13) to define an interface region therebetween (e.g., joint area; in Fig. 4C related in Figs.1-3, 5-13), the plurality of word lines including a plurality of dummy word lines being disposed adjacent the interface region (e.g., WLDU and WLDL; in Fig. 4C related in Figs. 1-3, 5-13), the controller configured to: instruct the memory apparatus to erase the memory cells in one of the first sub-block and the second sub-block individually in an erase operation (see paragraph [0082+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13); and instruct the memory apparatus to read the threshold voltage of the memory cells connected to one or more of the plurality of dummy word lines (see paragraph [0090+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13) and adjust based on the threshold voltage of the memory cells connected to which of the one of the first sub-block and the second sub-block is erased in the erase operation (see for example in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13). However, Penzo is silent with regard to adjust based on one or more of the plurality of dummy word lines relative to at least one dummy target voltage. In the same field of endeavor, Takekida, for example in Figs. 1-7, discloses to adjust based on one or more of the plurality of dummy word lines relative to at least one dummy target voltage (e.g., to adjust selected WL/WLD and unselected WL/WLD voltage; in Figs. 5-7 related in Figs. 1-4). It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Penzo such as word line zoned adaptive initial program voltage for non-volatile memory (see for example in Figs. 1-13 of Penzo) by incorporating the teaching of Takekida such as semiconductor storage device (see for example in Figs. 1-7 of Takekida), for the purpose of controlling the sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string (Takekida, see abstract). The structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 9 , the above Penzo/Takekida, combination discloses wherein each of the memory holes define a channel and the controller is further configured to instruct the memory apparatus to apply a plurality of erase voltage pulses of an erase voltage to the channel of the memory holes including the memory cells being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) each followed by an erase verify pulse of an erase verify voltage applied to ones of the plurality of word lines connected to the memory cells being erased to verify the memory cells are erased in an erase verify of the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 10 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage is selected to increase potential of the channel for a selected one of the first sub-block and the second sub-block during a program operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the memory cells of the selected one of the first sub-block and the second sub-block being programmed during the program operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 11 , the above Penzo/Takekida, combination discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes and at least one source-side select gate transistor on a source-side of each of the memory holes (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, the plurality of dummy word lines includes an upper dummy word line and a lower dummy word line disposed vertically below the upper dummy word line (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), and the controller is further configured to: instruct the memory apparatus to read the threshold voltage of the memory cells connected to the upper dummy word line using a predetermined dummy read level and adjust based on the threshold voltage of the memory cells connected to the upper dummy word line relative to the predetermined dummy read level in response to the first sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and instruct the memory apparatus to read the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and adjust based on the threshold voltage of the memory cells connected to the lower dummy word line relative to the predetermined dummy read level in response to the second sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 12 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the controller is further configured to: instruct the memory apparatus to begin erasing the memory cells in the second sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); instruct the memory apparatus to finish erasing the memory cells in the second sub-block in the erase operation; instruct the memory apparatus to read the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and count a lower dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determine whether the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); instruct the memory apparatus to program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and instruct the memory apparatus to program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding claim 13 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the controller (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) is further configured to: instruct the memory apparatus to begin erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); instruct the memory apparatus to finish erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); instruct the memory apparatus to read the threshold voltage of the memory cells connected to the upper dummy word line using the predetermined dummy read level and count an upper dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determine whether the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); instruct the memory apparatus to program the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and instruct the memory apparatus to program the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Also, the structure in of the prior art (Penzo and Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II). Regarding Independent Claim 14 , Penzo, for example in Figs. 1-13, discloses a method of operating a memory apparatus (see for example in Figs. 1-2 related in Figs. 3-13) including memory cells (e.g., memory cells; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) each connected to one of a plurality of word lines (e.g., word lines; in Figs. 4B, 4C, 4E, 4F related in Figs. 1-3, 5-13) and disposed in memory holes (see for example in Figs. 3-4 related in Figs. 1-2, 5-13) extending vertically through a stack of the plurality of word lines (see for example in Figs. 3-4 related in Figs. 1-2, 5-13), the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., data states; in Figs. 5-7 related in Figs. 1-4, 8-13), the memory cells form a block including a first sub-block (e.g., lower set of word lines; in Fig. 4C related in Figs. 1-3, 5-13) vertically below a second sub-block (e.g., upper set of word lines; in Figs. 4C related in Figs. 1-3, 5-13) to define an interface region therebetween (e.g., joint area; in Fig. 4C related in Figs.1-3, 5-13), the plurality of word lines including a plurality of dummy word lines being disposed adjacent the interface region (e.g., WLDU and WLDL; in Fig. 4C related in Figs. 1-3, 5-13), the method comprising the steps of: erasing the memory cells in one of the first sub-block and the second sub-block individually in an erase operation (see paragraph [0082+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13); and reading the threshold voltage of the memory cells connected to one or more of the plurality of dummy word lines (see paragraph [0090+]; in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13) and adjust based on the threshold voltage of the memory cells connected to at least one dummy target voltage and based on which of the one of the first sub-block and the second sub-block is erased in the erase operation (see for example in Fig. 2, 5-7 related in Figs. 1, 3-4, 8-13). However, Penzo is silent with regard to adjust based on one or more of the plurality of dummy word lines relative to at least one dummy target voltage. In the same field of endeavor, Takekida, for example in Figs. 1-7, discloses to adjust based on one or more of the plurality of dummy word lines relative to at least one dummy target voltage (e.g., to adjust selected WL/WLD and unselected WL/WLD voltage; in Figs. 5-7 related in Figs. 1-4). It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Penzo such as word line zoned adaptive initial program voltage for non-volatile memory (see for example in Figs. 1-13 of Penzo) by incorporating the teaching of Takekida such as semiconductor storage device (see for example in Figs. 1-7 of Takekida), for the purpose of controlling the sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string (Takekida, see abstract). Regarding claim 15 , the above Penzo/Takekida, combination discloses wherein each of the memory holes define a channel and the method further includes the step of applying a plurality of erase voltage pulses of an erase voltage to the channel of the memory holes including the memory cells being erased in the erase operation each followed (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above) by an erase verify pulse of an erase verify voltage applied to ones of the plurality of word lines connected to the memory cells being erased to verify the memory cells are erased in an erase verify of the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Regarding claim 16 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage is selected to increase potential of the channel for a selected one of the first sub-block and the second sub-block during a program operation, the memory cells of the selected one of the first sub-block and the second sub-block being programmed during the program operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Regarding claim 17 , the above Penzo/Takekida, combination discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes and at least one source-side select gate transistor on a source-side of each of the memory holes (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), the plurality of dummy word lines includes an upper dummy word line and a lower dummy word line disposed vertically below the upper dummy word line (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above), and the method further includes the steps of: reading the threshold voltage of the memory cells connected to the upper dummy word line using a predetermined dummy read level and adjusting based on the threshold voltage of the memory cells connected to the upper dummy word line relative to the predetermined dummy read level in response to the first sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and reading the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and adjusting based on the threshold voltage of the memory cells connected to the lower dummy word line relative to the predetermined dummy read level in response to the second sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Regarding claim 18 , the above Penzo/Takekida, combination discloses further including the steps of: adjusting the threshold voltage of the memory cells connected to the lower dummy word line in response to the first sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and adjusting the threshold voltage of the memory cells connected to the upper dummy word line in response to the second sub-block being erased in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Regarding claim 19 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the method further includes the steps of: beginning erasing the memory cells in the second sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); finishing erasing the memory cells in the second sub-block in the erase operation; reading the threshold voltage of the memory cells connected to the lower dummy word line using the predetermined dummy read level and counting a lower dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determining whether the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); programming the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and programming the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the lower dummy fail bit quantity of the memory cells connected to the lower dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Regarding claim 20 , the above Penzo/Takekida, combination discloses wherein the at least one dummy target voltage includes an upper dummy target voltage and a lower dummy target voltage, and the method further includes the steps of: beginning erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); finishing erasing the memory cells in the first sub-block in the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); reading the threshold voltage of the memory cells connected to the upper dummy word line using the predetermined dummy read level and counting an upper dummy fail bit quantity of the memory cells having the threshold voltage below the predetermined dummy read level immediately following the erase operation (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); determining whether the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than a predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); programming the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is not greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above); and programming the threshold voltage of the memory cells connected to the upper dummy word line to the upper dummy target voltage and the threshold voltage of the memory cells connected to the lower dummy word line to the lower dummy target voltage in response determining the upper dummy fail bit quantity of the memory cells connected to the upper dummy word line is greater than the predetermined dummy fail bit threshold (see for example in Figs. 1-2, 5-7 related in Figs. 3-4, 8-13 of Penzo and also see in Figs. 5-7 related in Figs. 1-4 of Takekida, as discussed above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THA-O H BUI/Primary Examiner, Art Unit 2825 06/12/2026 Application/Control Number: 18/980,921 Page 2 Art Unit: 2825
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