Prosecution Insights
Last updated: October 23, 2026
Application No. 18/981,015

INVERTER ARRANGEMENT FOR MONITORING THE TEMPERATURE OF POWER SEMICONDUCTORS

Non-Final OA §102
Filed
Dec 13, 2024
Priority
Dec 14, 2023 — DE 10 2023 212 656.7
Examiner
DE LEON DOMENECH, RAFAEL O
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ZF Friedrichshafen AG
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
442 granted / 502 resolved
+20.0% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
10 currently pending
Career history
509
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
44.2%
+4.2% vs TC avg
§102
35.0%
-5.0% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 502 resolved cases

Office Action

§102
DETAILED ACTION This Office action is in response to the application filed on December 13, 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Inventorship This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 13, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings were filed on December 13, 2024. These drawings are accepted by the Examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (U.S. Pub. No. 2023/0254976 A1). In re claim 1, Wang discloses (Figs. 1-8) an inverter assembly (50), comprising: at least one semiconductor package with external electrical connections (Para. 0031), and at least one external connecting pin (12) for a signal or control terminal; a printed circuit board (16) placed above and spaced apart from the semiconductor package (Para. 0029-0032), wherein the at least one connecting pin passes through a hole in the printed circuit board and is attached thereto (Figs. 6-8); and a temperature sensor (10) placed near the at least one connecting pin (12) on the printed circuit board, such that the temperature sensor can measure a temperature of a power semiconductor in the semiconductor package transferred to the connecting pin (Para. 0029-0034). In re claim 8, Wang discloses wherein the temperature sensor (10) is as close to the connecting pin (12) as possible without touching the connecting pin (Figs. 6-8). Allowable Subject Matter Claims 2-7 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding to claim 2, the prior art of record fails to disclose or suggest “wherein the temperature sensor is on an upper surface of the printed circuit board facing away from the semiconductor package, or on a lower surface of the printed circuit board facing toward the semiconductor package” in combination with other limitations of the claim. Claims 3-7 depend directly or indirectly from claim 2 and are, therefore, also objected at least for the same reasons set above. Regarding to claim 9, the prior art of record fails to disclose or suggest “wherein the temperature sensor is at a predefined distance to the connecting pin, and wherein there is at least one conductor path on the printed circuit board, which leads from the temperature sensor to the connecting pin and transfers heat” in combination with other limitations of the claim. Regarding to claim 10, the prior art of record fails to disclose or suggest “wherein the temperature sensor is a surface mount device (SMD” in combination with other limitations of the claim. Regarding to claim 11, the prior art of record fails to disclose or suggest “wherein the temperature sensor is connected to an evaluation unit in the inverter assembly, wherein the evaluation unit is configured to process temperatures measured by the temperature sensor such that the evaluation unit can detect when a predefined temperature has been exceeded” in combination with other limitations of the claim. Regarding to claim 12, the prior art of record fails to disclose or suggest “wherein a plastic component or plastic hybrid component that has a central hole is placed on a surface of the semiconductor package facing the printed circuit board, and wherein the temperature sensor is placed on the printed circuit board above the hole” in combination with other limitations of the claim. Regarding to claim 13, the prior art of record fails to disclose or suggest “a three-phase electric motor in a vehicle, wherein the power electronics comprises: the inverter assembly according to claim 1; and at least one electronic control unit connected to the electric motor and the inverter assembly” in combination with other limitations of the claim. Claim 14 depends directly from claim 13 and is, therefore, also objected at least for the same reasons set above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hammond Crystal can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Dec 13, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+10.7%)
2y 1m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 502 resolved cases by this examiner. Grant probability derived from career allowance rate.

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