Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bear et al (2022/0029838) in views of Sadate et al (6747507) and Ren et al (CN 106372539).
For claim 1, Bear teaches an integrated circuit device (abstract), comprising: a physical unclonable function (PUF) circuit distributed over multiple dies of the integrated circuit device (Bear teaches that typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks as Bear teaches in par.19), wherein the PUF circuit comprises: a current source circuit (Bear teaches that enabling measures to be taken by the package security controller when power is restored. These reactions to a security compromise of the package will occur even if the security breach was done when the device was completely without power and even if it is re-assembled before applying power as Bear teaches in par.45) and a ring oscillator circuit random variations of components of the PUF circuit (Bear teaches that Ring-oscillator based PUFs use propagation delay variations as their entropy source as Bear teaches in par.30).
Bear fails to teach that a current source circuit configured to source first, second, and third currents from a gated supply voltage, and to control the first, second, and third currents based on an analog voltage; a voltage control circuit configured to control the analog voltage based on the first and second currents, a ring oscillator circuit configured to output a clock having a frequency that is based on the third current and random variations of components of the PUF circuit.
Sadate teaches, similar system, that a current source circuit configured to source first, second, and third currents from a gated supply voltage, and to control the first, second, and third currents based on an analog voltage (Sadate teaches that current source with multiple paths that the current is distributed into from voltage supply as Sadate teaches in abstract, col.2, lines 15-33 and and shown in fig.4); a voltage control circuit configured to control the analog voltage based on the first and second currents ( Sadate teaches that amplifier having a first input coupled to the first transistor and to a gate of the second transistor, and a second input coupled to a control voltage node; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the third transistor and having a gate coupled to an output of the amplifier; a fifth transistor; a sixth transistor coupled in parallel with the fifth transistor; a seventh transistor coupled in series with the fifth transistor; and an eighth transistor coupled in series with the seventh transistor and having a gate coupled to a gate of the fourth transistor. In order to maintain the bias generator stability for. different biasing conditions, the feed-forward path is removed by diode connecting the second transistor instead of connecting the gate of the second transistor to the control voltage node as Sadate teaches in col.2, lines 15-33). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include current source with multiple current paths and voltage control circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
Ren teaches that a ring oscillator circuit configured to output a clock having a frequency that is based on the third current and random variations of components of the PUF circuit (Ren teaches that the safety of the variable frequency ring oscillator PUF designed by the invention is better than the traditional ring oscillator PUF and requiring high scene can be used for safety as Ren teaches in abstract). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include ring oscillator circuit configured to output a clock having a frequency as taught and suggested by Ren for the purpose of providing an improvement to establish the corresponding mathematical model, so as to greatly improve the safety of the PUF (Ren, abstract).
For claim 2, Bear, as modified by Sadate, and Ren, further teaches that wherein: a first one of the dies; and a second one of the dies comprises the current source circuit (Bear, par.19).
Bear fails to teach dies comprises the voltage control circuit and the ring oscillator circuit and one of the dies comprises the current source circuit.
Sadate teaches that dies comprises the voltage control circuit and the ring oscillator circuit and one of the dies comprises the current source circuit (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include voltage control circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 3, Bear, as modified by Sadate, and Ren, fails to teach wherein the first die further comprises a power gate circuit configured to provide the gated supply voltage to the second die.
Sadate further teaches that wherein the first die further comprises a power gate circuit configured to provide the gated supply voltage to the second die (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include voltage control circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 4, Bear, as modified by Sadate, and Ren, fails to teach wherein the voltage control circuit comprises: a first load configured to establish a first voltage based on the first current; a second load configured to establish a second voltage based on the second current; and a differential amplifier circuit configured to control the analog voltage based on the first and second voltages.
Sadate further teaches that wherein the voltage control circuit comprises: a first load configured to establish a first voltage based on the first current; a second load configured to establish a second voltage based on the second current; and a differential amplifier circuit configured to control the analog voltage based on the first and second voltages (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include voltage control circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 5, Bear, as modified by Sadate, and Ren, fails to teach wherein: the first load comprises a first resistor circuit in series with a first diode-connected transistor, in parallel with a second resistor circuit; and the second load comprises a second diode-connected transistor.
Sadate further teaches that wherein: the first load comprises a first resistor circuit in series with a first diode-connected transistor, in parallel with a second resistor circuit; and the second load comprises a second diode-connected transistor (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include load circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 6, Bear, as modified by Sadate, and Ren, fails to teach wherein the differential amplifier circuit comprises a differential-input operational transconductance amplifier.
Sadate further teaches that wherein the differential amplifier circuit comprises a differential-input operational transconductance amplifier (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include differential amplifier circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 7, Bear, as modified by Sadate, and Ren, fails to teach wherein the current source circuit comprises: a first transistor configured to source the first current from the gated supply voltage; a second transistor configured to source the second current from the gated supply voltage; and a ring oscillator current source circuit that comprises a third transistor configured to source the third current from the gated supply voltage; wherein gates of the first, second, and third transistors are controlled by the analog voltage.
Sadate further teaches that wherein the current source circuit comprises: a first transistor configured to source the first current from the gated supply voltage; a second transistor configured to source the second current from the gated supply voltage; and a ring oscillator current source circuit that comprises a third transistor configured to source the third current from the gated supply voltage; wherein gates of the first, second, and third transistors are controlled by the analog voltage (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include differential amplifier circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 8, Bear, as modified by Sadate, and Ren, fails to teach wherein: the PUF circuit is configurable to alter the frequency of the clock; and the integrated circuit device further comprises control circuitry to configure the PUF circuit.
Ren further teaches that wherein: the PUF circuit is configurable to alter the frequency of the clock; and the integrated circuit device further comprises control circuitry to configure the PUF circuit (abstract). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include ring oscillator circuit configured to output a clock having a frequency as taught and suggested by Ren for the purpose of providing an improvement to establish the corresponding mathematical model, so as to greatly improve the safety of the PUF (Ren, abstract).
For claim 9, Bear, as modified by Sadate, and Ren, fails to teach wherein the voltage control circuit comprises: multiple differential oscillator circuits configured to control respective analog voltages based on the first and second currents, wherein the analog voltages differ from one another due to random variations of circuit elements of the differential oscillator circuits; and selection circuitry configured to provide a selectable one of the analog voltages to the current source circuit based on a control from the control circuit.
Sadate further teaches that wherein the voltage control circuit comprises: multiple differential oscillator circuits configured to control respective analog voltages based on the first and second currents, wherein the analog voltages differ from one another due to random variations of circuit elements of the differential oscillator circuits; and selection circuitry configured to provide a selectable one of the analog voltages to the current source circuit based on a control from the control circuit (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include differential amplifier circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 10, Bear, as modified by Sadate, and Ren, fails to teach wherein the voltage control circuit comprises: a first load configured to establish a first voltage based on the first current, wherein the first load comprises a first resistor circuit in series with a first diode-connected transistor, in parallel with a second resistor circuit that comprises a bank of resistors, and selection circuitry configured to select one of more of the resistors of the bank of resistors based on a control from the control circuit; a second load configured to establish a second voltage based on the second current; and a differential amplifier circuit configured to control the analog voltage based on the first and second voltages.
Sadate further teaches that wherein the voltage control circuit comprises: a first load configured to establish a first voltage based on the first current, wherein the first load comprises a first resistor circuit in series with a first diode-connected transistor, in parallel with a second resistor circuit that comprises a bank of resistors, and selection circuitry configured to select one of more of the resistors of the bank of resistors based on a control from the control circuit; a second load configured to establish a second voltage based on the second current; and a differential amplifier circuit configured to control the analog voltage based on the first and second voltages (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include differential amplifier circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 11, Bear, as modified by Sadate, and Ren, fails to teach wherein the current source circuit comprises: a first transistor configured to source the first current from the gated supply voltage; a second transistor configured to source the second current from the gated supply voltage; and a ring oscillator current source circuit that comprises multiple transistors and selector circuitry configured to select one or more of the multiple transistors to source the third current from the gated supply voltage based on a control from the control circuitry; wherein gates of the first transistor, the second transistor, and selected ones of the multiple transistors are controlled by the analog voltage.
Sadate further teaches that wherein the current source circuit comprises: a first transistor configured to source the first current from the gated supply voltage; a second transistor configured to source the second current from the gated supply voltage; and a ring oscillator current source circuit that comprises multiple transistors and selector circuitry configured to select one or more of the multiple transistors to source the third current from the gated supply voltage based on a control from the control circuitry; wherein gates of the first transistor, the second transistor, and selected ones of the multiple transistors are controlled by the analog voltage (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include differential amplifier circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
For claim 12, Bear, as modified by Sadate, and Ren, fails to teach wherein the control circuitry is configured to: sequentially configure the PUF circuit in each of multiple configurations for respective periods of time to provide the clock with time-multiplexed frequencies.
Ren further teaches that wherein the control circuitry is configured to: sequentially configure the PUF circuit in each of multiple configurations for respective periods of time to provide the clock with time-multiplexed frequencies (abstract). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include with time-multiplexed frequencies as taught and suggested by Ren for the purpose of providing an improvement to establish the corresponding mathematical model, so as to greatly improve the safety of the PUF (Ren, abstract).
For claim 13, Bear, as modified by Sadate, and Ren, further teaches that a signature generator circuit configured to: determine a first bit value based on two or more of the time-multiplexed frequencies; determine additional bit values based on time-multiplexed frequencies of clocks generated by respective additional PUF circuits of the integrated circuit device; and construct a signature that is unique to the integrated circuit device based on the first bit value and the additional bit values (Bear teaches that generating and using a signature code, creating a decryption code (key), verifying by hardware (HW) if it detects tampering or if it finds evidence of potential tampering, alert HW or Software (SW) that it was attacked, derive or generate further per-assembly keys, and use for attestation of authenticity or other applications. In exemplary embodiment, the tampering alert is communicated to an external source and typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks. In one embodiment, this is achieved by using the minute manufacturing variations in the HIP and developing the raw values in a Soft IP block into a wide (multi-bit) key that can then be used to secure data at rest and data in motion using various encryption schemes as Bear teachers in par.19 and 29).
For claim 14, Bear, as modified by Sadate, and Ren, further teaches a signature generator circuit configured to: determine multiple bit values based on respective subsets of two or more of the time-multiplexed frequencies; and construct a signature that is unique to the integrated circuit device based on the multiple bit values (Bear teaches that generating and using a signature code, creating a decryption code (key), verifying by hardware (HW) if it detects tampering or if it finds evidence of potential tampering, alert HW or Software (SW) that it was attacked, derive or generate further per-assembly keys, and use for attestation of authenticity or other applications. In exemplary embodiment, the tampering alert is communicated to an external source and typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks. In one embodiment, this is achieved by using the minute manufacturing variations in the HIP and developing the raw values in a Soft IP block into a wide (multi-bit) key that can then be used to secure data at rest and data in motion using various encryption schemes as Bear teachers in par.19 and 29).
For claims 15 and 18, Bear teaches An integrated circuit device (abstract), comprising: a first die comprising and a signature generator circuit configured to determine a bit value based on a frequency of the clock, and to construct a signature of the integrated circuit device based on the bit value (Bear teaches that generating and using a signature code, creating a decryption code (key), verifying by hardware (HW) if it detects tampering or if it finds evidence of potential tampering, alert HW or Software (SW) that it was attacked, derive or generate further per-assembly keys, and use for attestation of authenticity or other applications. In exemplary embodiment, the tampering alert is communicated to an external source and typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks. In one embodiment, this is achieved by using the minute manufacturing variations in the HIP and developing the raw values in a Soft IP block into a wide (multi-bit) key that can then be used to secure data at rest and data in motion using various encryption schemes as Bear teachers in par.19 and 29).
Bear fails to teach that a voltage control circuit configured to control an analog voltage based on first and second currents, and further comprising a ring oscillator circuit configured to generate a clock based on a third current; a second die comprising a current source circuit configured to source the first and second currents and a third current from a gated supply voltage, and to control the first, second, and third currents based on the analog voltage.
Sadate further teaches a voltage control circuit configured to control an analog voltage based on first and second currents, a second die comprising a current source circuit configured to source the first and second currents and a third current from a gated supply voltage, and to control the first, second, and third currents based on the analog voltage (abstract) (fig.4) (col.2, lines 15-35). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include voltage control circuit as taught and suggested by Sadate for the purpose of providing an improvement in the stability of the Maneatis bias generator and the change in the circuit improves its stability without using capacitor and resistor, and maintaining the advantages for good substrate and supply rejections (Sadate, col.3, lines 13-18).
Ren further teaches that a ring oscillator circuit configured to generate a clock based on a third current; (abstract). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include with time-multiplexed frequencies as taught and suggested by Ren for the purpose of providing an improvement to establish the corresponding mathematical model, so as to greatly improve the safety of the PUF (Ren, abstract).
For claims 16 and 19, Bear, as modified by Sadate, and Ren, further teaches wherein: the integrated circuit device further comprises the signature generator circuit is further configured to determine the bit value based on two or more of the time-multiplexed (Bear teaches that generating and using a signature code, creating a decryption code (key), verifying by hardware (HW) if it detects tampering or if it finds evidence of potential tampering, alert HW or Software (SW) that it was attacked, derive or generate further per-assembly keys, and use for attestation of authenticity or other applications. In exemplary embodiment, the tampering alert is communicated to an external source and typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks. In one embodiment, this is achieved by using the minute manufacturing variations in the HIP and developing the raw values in a Soft IP block into a wide (multi-bit) key that can then be used to secure data at rest and data in motion using various encryption schemes as Bear teachers in par.19 and 29).
Bear fails to teach that control circuitry configured to sequentially configure one or more of the voltage control circuit and the current source circuit in each of multiple configurations for respective periods of time to provide the clock with time-multiplexed frequencies.
Ren further teaches that control circuitry configured to sequentially configure one or more of the voltage control circuit and the current source circuit in each of multiple configurations for respective periods of time to provide the clock with time-multiplexed frequencies (abstract). It would have been obvious to one ordinary skill in the art before effective filling date to modify Bear to include with time-multiplexed frequencies as taught and suggested by Ren for the purpose of providing an improvement to establish the corresponding mathematical model, so as to greatly improve the safety of the PUF (Ren, abstract).
For claims 17 and 20, Bear, as modified by Sadate, and Ren, further teaches wherein: the signature generator circuit is further configured to determine multiple bit values based on multiple respective subsets of the time-multiplexed frequencies, and to construct the signature of the integrated circuit device based on the bit values (Bear teaches that generating and using a signature code, creating a decryption code (key), verifying by hardware (HW) if it detects tampering or if it finds evidence of potential tampering, alert HW or Software (SW) that it was attacked, derive or generate further per-assembly keys, and use for attestation of authenticity or other applications. In exemplary embodiment, the tampering alert is communicated to an external source and typical PUF structure is comprised of cells that use the die-to-die variations in order to create a multi-bit value that is different per die even if the dies were manufactured on the same wafer using the same masks. In one embodiment, this is achieved by using the minute manufacturing variations in the HIP and developing the raw values in a Soft IP block into a wide (multi-bit) key that can then be used to secure data at rest and data in motion using various encryption schemes as Bear teachers in par.19 and 29).
For claim 18, see the rejections of claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYUB A MAYE whose telephone number is (571)270-5037. The examiner can normally be reached Monday-Friday 9AM-5PM.
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/AYUB A MAYE/Examiner, Art Unit 2436
/TRONG H NGUYEN/Primary Examiner, Art Unit 2436
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