Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Claims
Claims 1-20 are subject to examination.
Priority
The claim for domestic priorities as claimed in this application under 35 U.S.C. 119(e) is acknowledged.
This application is a CON of 18/412,344 01/12/2024 PAT 12200148
18/412,344 is a DIV of 17/208,894 03/22/2021 PAT 11902455
17/208,894 is a CON of 16/026,409 07/03/2018 PAT 10958453
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
The claims 1-20, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of Lu et al, U.S. Patent No. 12200148 in view of KOZICKI et al., 20200381372 and Gurrieri et al., 10103733.
Below is a comparison of limitations of the claims 1-20, of this application versus the claims 1-20 of Lu et al, Patent No. 12200148.
Claims of the Patent
Claims of this application
1. A method of generating a physical unclonable function (PUF) signature for a PUF cell
array, the method comprising:
generating a first PUF output under a normal operation condition of the PUF cell
array, wherein the PUF cell array comprises a plurality of bit cells;
creating a stressed operation condition for the PUF cell array;
generating a second PUF output under the stressed operation condition;
comparing the second PUF output with the first PUF output to identify at least one unstable
bit cell in the PUF cell array;
generating a mask array that masks the at least one unstable bit cell; and
filtering the first PUF output using the mask array to generate PUF signature.
2.
The method of claim 1, wherein the plurality of bit cells each comprises at least two access
transistors, at least two storage nodes, at least one enable transistor and two cross-coupled inverters.
3.
The method of claim 2, wherein the at least two access transistors are coupled between a
noise injector and the at least two storage nodes.
4.
The method of claim 2, wherein the at least two access transistors each comprise an NMOS
transistor and the at least one enable transistor comprises a PMOS transistor.
5.
The method of claim 2, further comprising:
turning off the at least one enable transistor by pulling up a first voltage, and
turning on the at least two access transistors by pulling up at least one second voltage.
6.
The method of claim 1, further comprising:
storing the first PUF output;
comparing the second PUF output with the first PUF output to identify at least one unstable
bit cell, wherein the second logical states of the at least one unstable bit cell in the first and the
second PUF outputs are different; and
storing an address of the at least one unstable bit cell in the mask array.
7.
The method of claim 1, further comprises:
filtering the first PUF output with the mask array to exclude a logical state of the at least
one unstable bit cell from the first PUF output to generate the PUF signature.
8.
A method of generating a physical unclonable function (PUF), the method comprising:
accessing a plurality of bit cells of a PUF cell array;
generating a first PUF output based on a normal operation condition of the PUF cell array;
introducing noise into the plurality of bit cells to create a stressed operation condition of
the PUF cell array;
generating a second PUF output under the stressed operation condition;
comparing the second PUF output with the first PUF output; and
storing at least one location of at least one unstable bit cell, the at least one unstable bit cell
having different states between the first and second PUF outputs; and
generating a mask array to exclude at least one logical state of the at least one unstable bit
cell to generate the PUF signature.
9.
The method of claim 8, wherein the plurality of bit cells each comprises at least two access
transistors, at least one enable transistor, at least two storage nodes and two cross-coupled inverters,
wherein the at least two storage nodes are pre-configured with substantially the same voltages
allowing each of the plurality of bit cells having a first metastable logical state.
10.
The method of claim 9, wherein the at least two access transistors each comprise an NMOS
transistor and the at least one enable transistor comprises a PMOS transistor.
11.
The method of claim 9, further comprising turning off the at least one enable transistor and
turning on the at least one two access transistors by pulling up a first voltage and at least one
second voltage, respectively, to write a first metastable logical state to each of the plurality of bit
cells.
12.
The method of claim 9, further comprising turning on the at least one enable transistor and
turning off the at least two access transistors by pulling down a first voltage and a at least one
second voltage, respectively, to allow the first metastable logical state to stabilize to the second
logical state in each of the plurality of bit cells.
13.
The method of claim 9, further comprising tuning signal timings of the turning on the at
least one enable transistor and the turning off the at least two access transistors of each of the
plurality of bit cells.
14.
The method of claim 8, wherein the first PUF output is stored in a copy array.
15.
The method of claim 8, further comprising providing a first voltage and at least one second
voltage to the plurality of bit cells through a delay circuit.
16.
A method of generating a physical unclonable function (PUF) signature, the method
comprising:
accessing a plurality of bit cells of a PUF cell array under a normal operation condition;
generating a first PUF output of the PUF cell array under the normal operation condition;
creating one or more stressed operation conditions for the plurality of bit cells;
generating a second PUF output when the PUF cell array is in the one or more stressed
operation conditions;
comparing the second PUF output with the first PUF output; and
storing at least one location of at least one unstable bit cell, respectively, the at least one
unstable bit cell having different states between the first and second PUF outputs; and
excluding at least one logical state of the at least one unstable bit cell to generate the PUF
signature.
17.
The method of claim 16, wherein the plurality of bit cells each comprises at least two access
transistors, at least one enable transistor, at least two storage nodes, the method further comprising
pre-configuring the at least two storage nodes with substantially the same voltages allowing each
of the plurality of bit cells having a first metastable logical state.
18.
The method of claim 17, wherein the one or more stressed operation conditions is created
by introducing noise into the plurality of bit cells.
19.
The method of claim 17, further comprising tuning signal timings of the turning on the at
least one enable transistor and the turning off the at least two access transistors of each of the
plurality of bit cells.
20.
The method of claim 16, further comprising providing a first voltage and at least one second
voltage to the plurality of bit cells through a delay circuit.
1. A method to configure a physical unclonable function (PUF) generator for generating a PUF signature, the method comprising: determining first logical states of a plurality of bit cells of a PUF cell array;
generating a first PUF output based on the first logical states;
introducing noise into the plurality of bit cells to create stressed operation conditions;
generating a second PUF output under the stressed operation conditions;
comparing the second PUF output with the first PUF output; and identifying at least one unstable bit cell that has a different state between the first and second PUF outputs; and generating a PUF signature that excludes a logic state of the at least one unstable bit cell.
2. The method of claim 1, wherein the plurality of bit cells each comprises at least two access transistors, at least two storage nodes, at least one enable transistor and two cross-coupled inverters.
3. The method of claim 2, wherein the at least two access transistors are coupled between a noise injector and the at least two storage nodes.
4. The method of claim 2, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor.
5. The method of claim 2, wherein the writing further comprising: turning off the at least one enable transistor by pulling up a first voltage, and turning on the at least two access transistors by pulling up at least one second voltage.
6. The method of claim 1, wherein the identifying further comprising: storing a first PUF output in a copy array; comparing a second PUF output with the first PUF output to identify at least one unstable bit cell, wherein the second logical states of the at least one unstable bit cell in the first and the second PUF outputs are different; and storing an address of the at least one unstable bit cell in a mask array.
7. The method of claim 1, wherein the generating further comprises: filtering a PUF output with a mask array to exclude the second logical state of the at least one unstable bit cell from the PUF output to generate the PUF signature.
8. A method of generating a physical unclonable function (PUF), the method comprising: accessing a plurality of bit cells of a PUF cell array to determine first logical states of each of the plurality of bit cells; generating a first PUF output based on the first logical states of the plurality of bit cells; introducing noise into the plurality of bit cells to cause the plurality of bit cells to have respective second logical states; generating a second PUF output based on the second logical states; comparing the second PUF output with the first PUF output; and storing at least one location of at least one unstable bit cell, the at least one unstable bit cell having different states between the first and second PUF outputs; and excluding at least one logical state of the at least one unstable bit cell to generate the PUF signature.
9. The method of claim 8, wherein the plurality of bit cells each comprises at least two access transistors, at least one enable transistor, at least two storage nodes and two cross-coupled inverters, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state.
10. The method of claim 9, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor.
11. The method of claim 9, further comprising turning off the at least one enable transistor and turning on the at least one two access transistors by pulling up a first voltage and at least one second voltage, respectively, to write a first metastable logical state to each of the plurality of bit cells.
12. The method of claim 9, further comprising turning on the at least one enable transistor and turning off the at least two access transistors by pulling down a first voltage and a at least one second voltage, respectively, to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.
13. The method of claim 9, further comprising tuning signal timings of the turning on the at least one enable transistor and the turning off the at least two access transistors of each of the plurality of bit cells.
14. The method of claim 8, wherein the introducing noise into the plurality of bit cells creates a stressed operation condition under which the second PUF output is generated.
15. The method of claim 8, further comprising providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit.
16. A method of generating a physical unclonable function (PUF), the method comprising: accessing a plurality of bit cells of a PUF cell array to determine first logical states of each of the plurality of bit cells; generating a first PUF output based on the first logical states of the plurality of bit cells; creating one or more stressed operation conditions for the plurality of bit cells to cause the plurality of bit cells to have respective second logical states; generating a second PUF output based on the second logical states; comparing the second PUF output with the first PUF output; and storing at least one location of at least one unstable bit cell, respectively, the at least one unstable bit cell having different states between the first and second PUF outputs; and excluding at least one logical state of the at least one unstable bit cell to generate the PUF signature.
17. The method of claim 16, wherein the plurality of bit cells each comprises at least two access transistors, at least one enable transistor, at least two storage nodes, the method further comprising pre-configuring the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state.
18. The method of claim 17, wherein creating the one or more stressed operation conditions comprises introducing noise into the plurality of bit cells.
19. The method of claim 17, further comprising tuning signal timings of the turning on the at least one enable transistor and the turning off the at least two access transistors of each of the plurality of bit cells.
20. The method of claim 16, further comprising providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit.
Claims 1, 8, 16 of this application contains, (which independent claims of Lu et al, U.S. Patent No. 12200148 do not mention about) normal operating condition of the PUF cell array, and filtering the first PUF output using the mask array, which is well-known in the art.
KOZICKI discloses, under a normal operation condition (
[0009] the invention provides a method of generating a secure key including providing an array, A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the patent claims to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could utilize the normal operation condition. It would enable generating a secure key using the array under the normal operation condition, abstract, para, 9.
Gurrieri discloses, filtering the first PUF output using the mask array (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the patent claims to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could utilize the filtering the first PUF output using the mask array. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, col., 10, 22-27.
The dependent claims 2-7, 9-15, 17-20 of this application are similar to this application.
Hence, claims 1-20 are subject to the double patenting rejections.
Specification
In paragraph [0001], status of co-pending applications should be made with --now copending-- and status of patent applications should be --now U.S. Patent number --.
Drawings
The figures submitted on the filing date of this application are acknowledged.
Information Disclosure Statement
An initialed and dated copy of the applicant’s IDS form 1449 (dated 12/13/24), is attached to the instant Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI et al., 20200381372 in view of Li, 20190342106 and Gurrieri et al., 10103733.
Referring to claim(s) 1, KOZICKI substantially discloses a method of generating a physical unclonable function (PUF) signature for a PUF cell array, the method comprising: generating a first PUF output under a normal operation condition of the PUF cell array, wherein the PUF cell array comprises a plurality of bit cells, to generate PUF signature
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range, as shown in FIG. 1. In this approach, the length of a random word is directly proportional to the size of the array.
creating a operation condition for the PUF cell array; generating a second PUF output under the operation condition, comparing the second PUF output with the first PUF output
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
[0057] In a cross-point array, all devices are essentially interconnected so each cell should typically be evaluated with all others placed in their off state to reduce currents through non-selected cells that may confuse the result.
KOZICKI do not disclose, which Li discloses, stressed condition (para 6, 91, 35) and to identify at least one unstable bit cell (para 95) in the PUF cell array (para 6, 91, 35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, para 95
KOZICKI and Li do not disclose, which Gurrieri discloses, filtering the first PUF output using the mask array (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide the filtering the first PUF output using the mask array. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Referring to claim(s) 6, Gurrieri discloses storing the first PUF output; comparing the second PUF output with the first PUF output to identify at least one unstable bit cell, wherein the second logical states of the at least one unstable bit cell in the first and the second PUF outputs are different; and
storing an address of the at least one unstable bit cell in the mask array
(
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
Referring to claim(s) 7, rejection of to generate the PUF signature is in claim 1. Gurrieri discloses filtering the first PUF output with the mask array to exclude a logical state of the at least one unstable bit cell from the first PUF output (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds. (36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit). (37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Claim(s) 2-5, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Li, Gurrieri and Jung et al., KR 20180032118 A.
Referring to claim(s) 2, KOZICKI, Li, Gurrieri do not disclose, which Jung discloses,
at least two storage nodes (
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
Referring to claim(s) 3, Li discloses, wherein the at least two access transistors are coupled between two entities (para 5), Jung discloses the at least two storage nodes (last five paras, page 4), a noise injector (stress injecting, claim 1)
Referring to claim(s) 4, Li discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 72, 40)
Referring to claim(s) 5, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage (para 51, 53)
Claim(s) 2, 4, 5, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Li, Gurrieri and Shifman et al., 20200007350.
Referring to claim(s) 2, KOZICKI, Li, Gurrieri do not disclose, which Shifman discloses,
at least two storage nodes, at least one enable transistor, two cross-coupled inverters, at least two access transistors (para 28, 5, 46, 40).
Shifman also discloses,
[0008] Imposed a small voltage difference, Delta, between VccL and VccR, during a calibration step. This caused bits which are unstable to be tilted either towards a zero or a one. FIG. 1C shows unstable bits in 100 noise runs. When Delta is negative, the bits are pushed towards a logic 1 state, and when Delta is positive, they are pushed towards a logic zero. The calibration step imposes positive and negative Delta's on the array, and any bit which does not change its state is deemed stable, and the unstable bits can be identified and disqualified, resulting in a 100% stable array without ECC.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable to eliminate unstable bits. This can drastically reduce or even eliminate the need for error correction codes (ECC), which makes the PUF array more secure, para 10.
Referring to claim(s) 4, Shifman discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 28, 41)
Referring to claim(s) 5, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage (para 51, 53)
Claim(s) 8, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman and Gurrieri.
Referring to claim(s) 8, KOZICKI substantially discloses A method of generating a physical unclonable function (PUF), the method comprising: accessing a plurality of bit cells of a PUF cell array;
generating a first PUF output based on a normal operation condition of the PUF cell array, to generate the PUF signature (
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range.
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
KOZICKI do not disclose, which Shifman discloses, introducing noise into the plurality of bit cells to create a stressed operation condition of the PUF cell array; generating a second PUF output under the stressed operation condition; comparing the second PUF output with the first PUF output, the at least one unstable bit cell having different states between the first and second PUF outputs (noise runs, para 8, 30, 7, 6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, para 8, 30, 7, 6.
KOZICKI and Shifman do not disclose, which Gurrieri discloses storing at least one location of at least one unstable bit cell
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
generating a mask array to exclude at least one logical state of the at least one unstable bit cell (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide to exclude at least one logical state of the at least one unstable bit cell. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Claim(s) 9, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman, Gurrieri, Li, Jung and Deng, 20110299349.
Referring to claim 9, KOZICKI, Shifman, Gurrieri do not disclose, which Jung discloses wherein the plurality of bit cells each comprises at least two storage nodes
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
KOZICKI, Shifman, Gurrieri, Jung do not disclose, which Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
KOZICKI, Shifman, Gurrieri, Li, Jung do not disclose, which Deng discloses, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state (para 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the voltages. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 10.
Referring to claim(s) 10, Li discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 72, 40)
Referring to claim(s) 11, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage, respectively (para 51, 53). Deng discloses,
to write a first metastable logical state to each of the plurality of bit cells (para 10).
Referring to claim(s) 12, Li and KOZICKI discloses, turning on the at least one enable transistor (Li, para 83, KOZICKI, para 51, 53) and turning off the at least two access transistors by pulling down a first voltage and a at least one second voltage (para 51, 53), respectively. Deng discloses to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.
Claim(s) 13, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman, Gurrieri, Li, Jung, Wu et al., 20140043886 and Hsu et al., 20180151219.
Referring to claim 13, KOZICKI, Shifman, Jung, Gurrieri do not disclose, which Wu discloses, tuning signal timings of the turning on the at least one enable transistor, para 52. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the tuning signal timings. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 52.
KOZICKI, Shifman, Jung, Gurrieri, Wu do not disclose, which Hsu discloses, the turning off the at least two access transistors of each of the plurality of bit cells (para 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the turning off the transistors. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 43.
Claim(s) 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman and Gurrieri and HASHIMOTO, 20170180477
The method of claim 14, KOZICKI in view of Shifman and Gurrieri do not disclose, which HASHIMOTO discloses wherein the first PUF output is stored in a copy array (para 112-116). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the copy array. The copy array would enable storing state of each of one or more of bit cells for analysis, para 112-116.
Claim(s) 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman and Gurrieri and Jung et al., Jung 2, 10224087.
Referring to claim 15, KOZICKI in view of Shifman and Gurrieri do not disclose, which Jung 2 discloses providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit. (col., 22, lines 2-16, 5-64). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the delay circuit. The delay circuit would enable delaying an operation such that the voltage is delayed so that the operation condition is no longer a normal operation for the testing, col., 22, lines 2-16, 5-64.
Claim(s) 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman and Gurrieri.
Referring to claim(s) 8, KOZICKI substantially discloses a method of generating a physical unclonable function (PUF) signature, the method comprising: accessing a plurality of bit cells of a PUF cell array under a normal operation condition; generating a first PUF output of the PUF cell array under the normal operation condition, to generate the PUF signature (
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range.
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
KOZICKI do not disclose, which Shifman discloses, creating one or more stressed operation conditions for the plurality of bit cells; generating a second PUF output when the PUF cell array is in the one or more stressed operation conditions; comparing the second PUF output with the first PUF output, the at least one unstable bit cell having different states between the first and second PUF outputs (para 30, 7, 8, 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, para 30, 7, 8, 6.
KOZICKI and Shifman do not disclose, which Gurrieri discloses storing at least one location of at least one unstable bit cell, respectively
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
excluding at least one logical state of the at least one unstable bit cell (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide to exclude at least one logical state of the at least one unstable bit cell. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Claim(s) 17, 18, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman, Gurrieri, Li, Jung and Deng, 20110299349.
Referring to claim 17, KOZICKI, Shifman, Gurrieri do not disclose, which Jung discloses wherein the plurality of bit cells each comprises at least two storage nodes
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
KOZICKI, Shifman, Gurrieri, Jung do not disclose, which Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
KOZICKI, Shifman, Gurrieri, Li, Jung do not disclose, which Deng discloses, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state (para 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the voltages. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 10.
Referring to claim 18, Shifman discloses, wherein the one or more stressed operation conditions is created by introducing noise into the plurality of bit cells (noise runs, para 8, 30, 7, 6).
Claim(s) 19, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman, Gurrieri, Li, Jung, Deng, Wu, and Hsu
Referring to claim 19, KOZICKI, Shifman, Jung, Deng, Gurrieri do not disclose, which Wu discloses, tuning signal timings of the turning on the at least one enable transistor, para 52. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the tuning signal timings. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 52.
KOZICKI, Shifman, Jung, Gurrieri, Deng, Wu do not disclose, which Hsu discloses, the turning off the at least two access transistors of each of the plurality of bit cells (para 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the turning off the transistors. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 43.
Claim(s) 20, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of Shifman, Gurrieri and Jung et al., Jung 2, 10224087.
Referring to claim 20, KOZICKI in view of Shifman and Gurrieri do not disclose, which Jung 2 discloses providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit. (col., 22, lines 2-16, 5-64). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the delay circuit. The delay circuit would enable delaying an operation such that the voltage is delayed so that the operation condition is no longer a normal operation for the testing, col., 22, lines 2-16, 5-64.
Claim(s) 1, 6, 7, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI et al., 20200381372 in view of AZUMA et al., JP 2017004587 A and Gurrieri et al., 10103733.
Referring to claim(s) 1, KOZICKI substantially discloses a method of generating a physical unclonable function (PUF) signature for a PUF cell array, the method comprising: generating a first PUF output under a normal operation condition of the PUF cell array, wherein the PUF cell array comprises a plurality of bit cells, to generate PUF signature
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range, as shown in FIG. 1. In this approach, the length of a random word is directly proportional to the size of the array.
creating a operation condition for the PUF cell array; generating a second PUF output under the operation condition, comparing the second PUF output with the first PUF output
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
[0057] In a cross-point array, all devices are essentially interconnected so each cell should typically be evaluated with all others placed in their off state to reduce currents through non-selected cells that may confuse the result.
KOZICKI do not disclose, which AZUMA discloses, stressed condition and to identify at least one unstable bit cell in the PUF cell array (
random noise is generated in a source-drain current by applying a pulse voltage to a gate electrode, and a random number is generated from the random noise, last 4th para, page 2
The initial state refers to a state where the resistance value is in an initial resistance value range that does not overlap with any of the variable resistance value ranges. The memory cell in the initial state does not enter the variable state unless a forming stress, which is an electrical stress that changes the state to the variable state, is applied. For example, the forming stress may be a cumulative stress. In this case, when the accumulated amount of stress exceeds a predetermined amount, the initial state is changed to the variable state. The memory cell 91 may not be an element that can take an initial state, 6th para page 8.
the memory cell can be in a variable state by applying a voltage pulse as a forming stress, 1st para, page 11
Whether or not the electrical stress is forming stress depends on whether or not the target memory cell 91 changes from the initial state to the variable state. The condition for the target memory cell 91 to change from the initial state to the variable state varies for each memory cell 91, 4th para, page 13
The special write mode can be described, for example, as a case in which the high resistance pulse is replaced with the first electrical stress and the low resistance pulse is replaced with the second electrical stress with respect to the normal write mode described above. For example, the voltage V .sub.H of the high resistance pulse is replaced with the voltage V .sub.H SP of the first electrical stress, and the voltage V .sub.L of the low resistance pulse is replaced with the voltage V .sub.L SP of the second electrical stress. Pulse width TP .sub.H high resistance pulse is replaced by a pulse width TP .sub.H SP of the first electrical stress pulse width TP .sub.L of low resistance pulse is replaced by a pulse width TP .sub.L SP of the second electric stress. The second electrical stress is an example of forming stress. Note that when information (for example, “0”) is assigned to an initial state memory cell to which no electrical stress is applied, the first electrical stress may not be applied. In other words, in the first electrical stress, the voltage V .sub.H SP may be 0 V and the pulse width TP .sub.H SP may be 0 nSec. Each of the first electrical stress and the second electrical stress may have a single voltage pulse width or may include a plurality of voltage pulses, 4th para, page 33)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, 6th para page 8
KOZICKI and AZUMA do not disclose, which Gurrieri discloses, filtering the first PUF output using the mask array (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide the filtering the first PUF output using the mask array. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Referring to claim(s) 6, Gurrieri discloses storing the first PUF output; comparing the second PUF output with the first PUF output to identify at least one unstable bit cell, wherein the second logical states of the at least one unstable bit cell in the first and the second PUF outputs are different; and
storing an address of the at least one unstable bit cell in the mask array
(
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
Referring to claim(s) 7, rejection of to generate the PUF signature is in claim 1. Gurrieri discloses filtering the first PUF output with the mask array to exclude a logical state of the at least one unstable bit cell from the first PUF output (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds. (36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit). (37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Claim(s) 2-5, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Li, Gurrieri and Jung et al., KR 20180032118 A.
Referring to claim(s) 2, KOZICKI, Azuma, Gurrieri do not disclose, which Jung discloses,
at least two storage nodes (
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
Referring to claim(s) 3, Li discloses, wherein the at least two access transistors are coupled between two entities (para 5), Jung discloses the at least two storage nodes (last five paras, page 4), a noise injector (stress injecting, claim 1)
Referring to claim(s) 4, Li discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 72, 40)
Referring to claim(s) 5, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage (para 51, 53)
Claim(s) 2, 4, 5, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Li, Gurrieri and Shifman et al., 20200007350.
Referring to claim(s) 2, KOZICKI, Li, AZUMA, Gurrieri do not disclose, which Shifman discloses,
at least two storage nodes, at least one enable transistor, two cross-coupled inverters, at least two access transistors (para 28, 5, 46, 40).
Shifman also discloses,
[0008] Imposed a small voltage difference, Delta, between VccL and VccR, during a calibration step. This caused bits which are unstable to be tilted either towards a zero or a one. FIG. 1C shows unstable bits in 100 noise runs. When Delta is negative, the bits are pushed towards a logic 1 state, and when Delta is positive, they are pushed towards a logic zero. The calibration step imposes positive and negative Delta's on the array, and any bit which does not change its state is deemed stable, and the unstable bits can be identified and disqualified, resulting in a 100% stable array without ECC.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable to eliminate unstable bits. This can drastically reduce or even eliminate the need for error correction codes (ECC), which makes the PUF array more secure, para 10.
Referring to claim(s) 4, Shifman discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 28, 41)
Referring to claim(s) 5, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage (para 51, 53)
Claim(s) 8, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA and Gurrieri.
Referring to claim(s) 8, KOZICKI substantially discloses A method of generating a physical unclonable function (PUF), the method comprising: accessing a plurality of bit cells of a PUF cell array;
generating a first PUF output based on a normal operation condition of the PUF cell array, to generate the PUF signature (
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range.
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
KOZICKI do not disclose, which AZUMA discloses, introducing noise into the plurality of bit cells to create a stressed operation condition of the PUF cell array; generating a second PUF output under the stressed operation condition; comparing the second PUF output with the first PUF output, the at least one unstable bit cell having different states between the first and second PUF outputs (
random noise is generated in a source-drain current by applying a pulse voltage to a gate electrode, and a random number is generated from the random noise, last 4th para, page 2
The initial state refers to a state where the resistance value is in an initial resistance value range that does not overlap with any of the variable resistance value ranges. The memory cell in the initial state does not enter the variable state unless a forming stress, which is an electrical stress that changes the state to the variable state, is applied. For example, the forming stress may be a cumulative stress. In this case, when the accumulated amount of stress exceeds a predetermined amount, the initial state is changed to the variable state. The memory cell 91 may not be an element that can take an initial state, 6th para page 8.
the memory cell can be in a variable state by applying a voltage pulse as a forming stress, 1st para, page 11
Whether or not the electrical stress is forming stress depends on whether or not the target memory cell 91 changes from the initial state to the variable state. The condition for the target memory cell 91 to change from the initial state to the variable state varies for each memory cell 91, 4th para, page 13
The special write mode can be described, for example, as a case in which the high resistance pulse is replaced with the first electrical stress and the low resistance pulse is replaced with the second electrical stress with respect to the normal write mode described above. For example, the voltage V .sub.H of the high resistance pulse is replaced with the voltage V .sub.H SP of the first electrical stress, and the voltage V .sub.L of the low resistance pulse is replaced with the voltage V .sub.L SP of the second electrical stress. Pulse width TP .sub.H high resistance pulse is replaced by a pulse width TP .sub.H SP of the first electrical stress pulse width TP .sub.L of low resistance pulse is replaced by a pulse width TP .sub.L SP of the second electric stress. The second electrical stress is an example of forming stress. Note that when information (for example, “0”) is assigned to an initial state memory cell to which no electrical stress is applied, the first electrical stress may not be applied. In other words, in the first electrical stress, the voltage V .sub.H SP may be 0 V and the pulse width TP .sub.H SP may be 0 nSec. Each of the first electrical stress and the second electrical stress may have a single voltage pulse width or may include a plurality of voltage pulses, 4th para, page 33
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, para 8, 30, 7, 6.
KOZICKI and AZUMA do not disclose, which Gurrieri discloses storing at least one location of at least one unstable bit cell
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
generating a mask array to exclude at least one logical state of the at least one unstable bit cell (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide to exclude at least one logical state of the at least one unstable bit cell. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Claim(s) 9, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Gurrieri, Li, Jung and Deng, 20110299349.
Referring to claim 9, KOZICKI, AZUMA, Gurrieri do not disclose, which Jung discloses wherein the plurality of bit cells each comprises at least two storage nodes
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
KOZICKI, AZUMA, Gurrieri, Jung do not disclose, which Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
KOZICKI, AZUMA, Gurrieri, Li, Jung do not disclose, which Deng discloses, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state (para 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the voltages. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 10.
Referring to claim(s) 10, Li discloses, wherein the at least two access transistors each comprise an NMOS transistor and the at least one enable transistor comprises a PMOS transistor (para 72, 40)
Referring to claim(s) 11, Li and KOZICKI discloses, turning off the at least one enable transistor by pulling up a first voltage (Li, para 83, KOZICKI, para 51, 53), and turning on the at least two access transistors by pulling up at least one second voltage, respectively (para 51, 53). Deng discloses,
to write a first metastable logical state to each of the plurality of bit cells (para 10).
Referring to claim(s) 12, Li and KOZICKI discloses, turning on the at least one enable transistor (Li, para 83, KOZICKI, para 51, 53) and turning off the at least two access transistors by pulling down a first voltage and a at least one second voltage (para 51, 53), respectively. Deng discloses to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.
Claim(s) 13, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Gurrieri, Li, Jung, Wu et al., 20140043886 and Hsu et al., 20180151219.
Referring to claim 13, KOZICKI, AZUMA, Jung, Gurrieri do not disclose, which Wu discloses, tuning signal timings of the turning on the at least one enable transistor, para 52. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the tuning signal timings. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 52.
KOZICKI, AZUMA, Jung, Gurrieri, Wu do not disclose, which Hsu discloses, the turning off the at least two access transistors of each of the plurality of bit cells (para 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the turning off the transistors. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 43.
Claim(s) 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA and Gurrieri and HASHIMOTO, 20170180477
The method of claim 14, KOZICKI in view of AZUMA and Gurrieri do not disclose, which HASHIMOTO discloses wherein the first PUF output is stored in a copy array (para 112-116). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the copy array. The copy array would enable storing state of each of one or more of bit cells for analysis, para 112-116.
Claim(s) 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA and Gurrieri and Jung et al., Jung 2, 10224087.
Referring to claim 15, KOZICKI in view of AZUMA and Gurrieri do not disclose, which Jung 2 discloses providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit. (col., 22, lines 2-16, 5-64). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the delay circuit. The delay circuit would enable delaying an operation such that the voltage is delayed so that the operation condition is no longer a normal operation for the testing, col., 22, lines 2-16, 5-64.
Claim(s) 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA and Gurrieri.
Referring to claim(s) 8, KOZICKI substantially discloses a method of generating a physical unclonable function (PUF) signature, the method comprising: accessing a plurality of bit cells of a PUF cell array under a normal operation condition; generating a first PUF output of the PUF cell array under the normal operation condition, to generate the PUF signature (
(A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices, abstract)
[0009] the invention provides a method of generating a secure key including providing an array, which includes a plurality of copper lines and a plurality of lines including W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines being positioned perpendicular to the plurality of copper lines, where a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines
PMC Arrays and PUFs
[0034] PUFs can strengthen the authentication methods of IoT elements, because they act as “digital signatures” of the hardware
The authentication is granted when the rate of correct matching responses is statistically high enough. PUFs can be generated with several components, such as ring oscillators and circuits with gate delays with field-programmable gate array (FPGA), static random access memories (SRAMs), sensors and microelectromechanical systems (MEMS) devices, Flash memories, magnetic memories, and various resistive random access memory (RAM) components.
[0037] PMC devices exhibit subtle random differences in operational parameters from cell to cell, due to the stochastic nature of the formation of the conducting pathway. The voltage, for example, at which the devices transition from a high resistance off state to some low resistance on state, the set voltage, varies randomly across an array of PMCs. This parameter can be partitioned into ranges representing logic 0 and logic 1, with the possibility of intermediate states being defined in an intervening range.
[0035] However, PUFs can have (i) a lack of stability of the physical parameters that creates high CRP error rates due to noisy conditions, and (ii) insufficient secret properties of the PUFs that make them vulnerable through side channel analysis by hackers. PUFs based on existing technologies often struggle to deliver in these two areas, and this is because these two limitations are often in conflict with each other: strong PUFs can have low CRP error rates but be too easy to analyze, while weak PUFs can have high CRP error rates and be well protected from side channel analysis. PMCs are attractive because their cells operate at extremely low voltage and low power, below the detectable level of side channel analysis.
KOZICKI do not disclose, which AZUMA discloses, creating one or more stressed operation conditions for the plurality of bit cells; generating a second PUF output when the PUF cell array is in the one or more stressed operation conditions; comparing the second PUF output with the first PUF output, the at least one unstable bit cell having different states between the first and second PUF outputs (
random noise is generated in a source-drain current by applying a pulse voltage to a gate electrode, and a random number is generated from the random noise, last 4th para, page 2
The initial state refers to a state where the resistance value is in an initial resistance value range that does not overlap with any of the variable resistance value ranges. The memory cell in the initial state does not enter the variable state unless a forming stress, which is an electrical stress that changes the state to the variable state, is applied. For example, the forming stress may be a cumulative stress. In this case, when the accumulated amount of stress exceeds a predetermined amount, the initial state is changed to the variable state. The memory cell 91 may not be an element that can take an initial state, 6th para page 8.
the memory cell can be in a variable state by applying a voltage pulse as a forming stress, 1st para, page 11
Whether or not the electrical stress is forming stress depends on whether or not the target memory cell 91 changes from the initial state to the variable state. The condition for the target memory cell 91 to change from the initial state to the variable state varies for each memory cell 91, 4th para, page 13
The special write mode can be described, for example, as a case in which the high resistance pulse is replaced with the first electrical stress and the low resistance pulse is replaced with the second electrical stress with respect to the normal write mode described above. For example, the voltage V .sub.H of the high resistance pulse is replaced with the voltage V .sub.H SP of the first electrical stress, and the voltage V .sub.L of the low resistance pulse is replaced with the voltage V .sub.L SP of the second electrical stress. Pulse width TP .sub.H high resistance pulse is replaced by a pulse width TP .sub.H SP of the first electrical stress pulse width TP .sub.L of low resistance pulse is replaced by a pulse width TP .sub.L SP of the second electric stress. The second electrical stress is an example of forming stress. Note that when information (for example, “0”) is assigned to an initial state memory cell to which no electrical stress is applied, the first electrical stress may not be applied. In other words, in the first electrical stress, the voltage V .sub.H SP may be 0 V and the pulse width TP .sub.H SP may be 0 nSec. Each of the first electrical stress and the second electrical stress may have a single voltage pulse width or may include a plurality of voltage pulses, 4th para, page 33)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide identifying bit cell state in the stressed condition. The undesired manner logic state for the bit cells would enable knowing of other/which cells that did not fall to undesired states during the stressed condition, and being stable for such operating conditions, 4th para, page 33.
KOZICKI and AZUMA do not disclose, which Gurrieri discloses storing at least one location of at least one unstable bit cell, respectively
(28) During operation of the bit-exclusion circuit 105, a plurality of raw PUF bits 203, that respectively correspond to the N PUF elements of the N-bit PUF array 103, are subjected to the bit-exclusion operation, based on the PUF mask 202. The generated raw PUF bits 203, that comprise a stream of N raw bits, are shown in FIG. 2 and are sorted into stable bits and unstable bits based on the bit-exclusion width 201a. The bit exclusion operation 204 excludes the unstable bits from the plurality of raw PUF bits 203, based on the PUF mask 202, and generates the error-free stable bit stream comprising a plurality of stable PUF bits 205. Col., 5, lines 28-35
(62) One of the major benefits of using the Monte Carlo simulations is to model the unstable bits in the IC-PUFs in order to know where the upper and lower thresholds of the bit-exclusion width will need to be set, and finally to be certain of how many raw PUF bits are needed in order to yield a desired number of stable bits. (63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa.(64) The total number of flipped bits decreases exponentially as the bit-exclusion width 201a is increased (e.g., the upper bound of the bit-exclusion width is increased and the lower bound of the bit-exclusion width is moved lower). In this Monte Carlo simulation of one hundred IC-PUFs, a bit-exclusion width of approximately 200 mV is needed to exclude the error bits (such as the bits that flip) and generate a stable, reliable PUF bit stream. Ideally, there would be no flipped bits in a PUF output under varying input voltages and operating temperatures. Col., 10, 22-37.
excluding at least one logical state of the at least one unstable bit cell (
(38) A technique that is used to yield more stable bits is to incorporate an upper threshold for the exclusion width 201a that is greater than approximately ½AVDD and a lower threshold for the exclusion width 201a that is less than approximately ½AVDD. The upper and lower thresholds are used to generate stable bits by excluding PUF output voltages that fall within the exclusion width 201a created by the upper and lower thresholds.
(36) On the other hand, if the channel resistance of the NMOS transistor N3 is greater than that of the PMOS transistor P3, then the potential on the VPUFOUT terminal will be greater than ½AVDD. A PUF-bit can be generated by comparing the PUF output voltage (VPUFOUT) to ½AVDD. If VPUFOUT is greater than ½AVDD, then the PUF-bit is a binary “1” (e.g., a logical-1 bit) and if VPUFOUT is less than ½AVDD, then the PUF-bit is a binary “0” (e.g., a logical-0 bit).
(37) The N-bit PUF array 103 is realized by building an array of N PUF elements (or unit cells) and using the addressing scheme to address each PUF element of the array of N PUF elements. As described above with respect to FIG. 2, one or more PUF elements, of the N-bit PUF array 103, will generate unstable PUF bits (e.g., the first PUF element may generate a logical “1” bit sometimes and a logical “0” bit at other times) based on how close their respective PUF output voltages, VPUFOUT, are to ½AVDD and how the output voltage, VPUFOUT, varies with power supply and temperature fluctuations. Therefore, the N-bit PUF array 103 will typically generate fewer than N stable bits. Col., 6, line 52 – col., 7, line 11
(41) To drive the PUF circuit of FIG. 3, a bias voltage generator is required to generate the VBP and VBN voltages. Raw output voltage VPUFOUT will be categorized into a logical “0” bit or a logical “1” bit based on comparing a magnitude of the raw output voltage VPUFOUT to the exclusion width 201a. A resulting raw PUF output bit (e.g., a first raw PUF output bit of the plurality of raw PUF bits 203 of FIG. 2) will be used in the bit-exclusion process 204 described earlier with respect to FIG. 2 to generate a stable PUF output bit (e.g., a first stable PUF bit of the plurality of stable PUF bits 205). Col., 7, lines 30-38
(63) The total number of flipped-bits, for a selected exclusion width, is estimated based on comparing an output PUF bit-string of a single IC-PUF over many interrogations and across varying input voltages and operating temperatures. The purpose of the comparison is to determine whether any of the bits in the IC-PUF's bit-string flip. For example, the comparison determines whether a logical 1 bit flips and becomes a logical 0 bit and vice versa. Col., 10, 22-27.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide to exclude at least one logical state of the at least one unstable bit cell. It would enable generating a secure key / PUF signature using only the stable bits and excluding the mask array having unstable bits, Col., 10, 22-27.
Claim(s) 17, 18, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Gurrieri, Li, Jung and Deng, 20110299349.
Referring to claim 17, KOZICKI, AZUMA, Gurrieri do not disclose, which Jung discloses wherein the plurality of bit cells each comprises at least two storage nodes
The first data storage node DS 1 may be located between the first pass gate transistor PGL 1 and one
end of the first and second inverters IN1 and IN2.
The second data storage node DS2 may be located between the second pass gate transistor PGL2
and one end of the first and second inverters IN1 and IN2.
The first pass gate transistor PGL 1 according to an embodiment of the present invention may be
connected to the first data storage node DS1 of the first and second inverters IN1 and IN2.
The second pass gate transistor PGL2 according to an embodiment of the present invention may be
connected to the second data storage node DS2 of the second and second inverters IN1 and IN2., last five paras, page 4.
at least one enable transistor (write enable transistor (fourth last para, page 5)
two cross-coupled inverters. (last seventh para, page 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the above well-known components. It would enable generating output knowing the bits enhances dynamic characteristics in low supply voltage, abstract.
KOZICKI, AZUMA, Gurrieri, Jung do not disclose, which Li discloses, at least two access transistors (para 5)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the access transistors. It would enable connecting the storage nodes to the bit lines during read and write operations, para 5.
KOZICKI, AZUMA, Gurrieri, Li, Jung do not disclose, which Deng discloses, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state (para 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the voltages. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 10.
Referring to claim 18, AZUMA discloses, wherein the one or more stressed operation conditions is created by introducing noise into the plurality of bit cells (
random noise is generated in a source-drain current by applying a pulse voltage to a gate electrode, and a random number is generated from the random noise, last 4th para, page 2
The initial state refers to a state where the resistance value is in an initial resistance value range that does not overlap with any of the variable resistance value ranges. The memory cell in the initial state does not enter the variable state unless a forming stress, which is an electrical stress that changes the state to the variable state, is applied. For example, the forming stress may be a cumulative stress. In this case, when the accumulated amount of stress exceeds a predetermined amount, the initial state is changed to the variable state. The memory cell 91 may not be an element that can take an initial state, 6th para page 8.
the memory cell can be in a variable state by applying a voltage pulse as a forming stress, 1st para, page 11
Whether or not the electrical stress is forming stress depends on whether or not the target memory cell 91 changes from the initial state to the variable state. The condition for the target memory cell 91 to change from the initial state to the variable state varies for each memory cell 91, 4th para, page 13
The special write mode can be described, for example, as a case in which the high resistance pulse is replaced with the first electrical stress and the low resistance pulse is replaced with the second electrical stress with respect to the normal write mode described above. For example, the voltage V .sub.H of the high resistance pulse is replaced with the voltage V .sub.H SP of the first electrical stress, and the voltage V .sub.L of the low resistance pulse is replaced with the voltage V .sub.L SP of the second electrical stress. Pulse width TP .sub.H high resistance pulse is replaced by a pulse width TP .sub.H SP of the first electrical stress pulse width TP .sub.L of low resistance pulse is replaced by a pulse width TP .sub.L SP of the second electric stress. The second electrical stress is an example of forming stress. Note that when information (for example, “0”) is assigned to an initial state memory cell to which no electrical stress is applied, the first electrical stress may not be applied. In other words, in the first electrical stress, the voltage V .sub.H SP may be 0 V and the pulse width TP .sub.H SP may be 0 nSec. Each of the first electrical stress and the second electrical stress may have a single voltage pulse width or may include a plurality of voltage pulses, 4th para, page 33).
Claim(s) 19, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Gurrieri, Li, Jung, Deng, Wu, and Hsu
Referring to claim 19, KOZICKI, AZUMA, Jung, Deng, Gurrieri do not disclose, which Wu discloses, tuning signal timings of the turning on the at least one enable transistor, para 52. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the tuning signal timings. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 52.
KOZICKI, AZUMA, Jung, Gurrieri, Deng, Wu do not disclose, which Hsu discloses, the turning off the at least two access transistors of each of the plurality of bit cells (para 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the turning off the transistors. It would enable creating an unstable logic level to check if the circuit acts in an unpredictable ways or not, para 43.
Claim(s) 20, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZICKI in view of AZUMA, Gurrieri and Jung et al., Jung 2, 10224087.
Referring to claim 20, KOZICKI in view of AZUMA and Gurrieri do not disclose, which Jung 2 discloses providing a first voltage and at least one second voltage to the plurality of bit cells through a delay circuit. (col., 22, lines 2-16, 5-64). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by KOZICKI to implement these limitations and also one of ordinary skill in the art would have been motivated to do so because it could provide utilizing the delay circuit. The delay circuit would enable delaying an operation such that the voltage is delayed so that the operation condition is no longer a normal operation for the testing, col., 22, lines 2-16, 5-64.Conclusion
Pertinent prior arts: Kim et al., 20190304527, abstract, figure 1.
The claims of this application are similar to the parent application, which is now allowed. See D.P. rejections. Since, new prior arts are available, such arts are used for the rejections of such claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARESH PATEL whose telephone number is (571)272-3973. The examiner can normally be reached on M-F 9-5:30.
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/HARESH N PATEL/Primary Examiner, Art Unit 2496
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