DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 12/13/24.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With respect to claim 1, the recitation “an output voltage” in line 14 and 17-18 are indefinite because it’s unclear if it’s the same as or in addition to the “output voltage” of lines 2, 4, 6 and 9.
Claims 2-12 contain the indefiniteness of claim 1.
With respect to claims 7, and 19 the recitation “a DC voltage” is indefinite because it’s unclear if it’s the same as or in addition to the output voltage of claim 1.
With respect to claim 9, the recitation “the first loop further includes a dedicated output component configured to transmit a voltage reference signal configured to provide a setpoint for a voltage regulator control scheme” is indefinite. The specification cites the output component as output voltage 506. Its unclear how that is a reference voltage. The first loop does have a reference voltage generator and reference voltage that would set a point for comparison with the output voltage at the error amplifier.
With respect to claim 20 the recitation “an/the output voltage of the first loop the output voltage of the first loop” is indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-10, 13-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al 20090001952.
With respect to claims 1 and 13, figures 6-8 of Chang et al. disclose an electronic system, comprising: a plurality of voltage regulation loops [616, 618, C2, C3, R3 and 604,608] configured to stabilize [abstract] an output voltage [Vo] of an electronic circuit, including:
a first loop [616, 618, C2,C3,R3] configured to regulate the output voltage within the electronic circuit during transient voltage conditions, comprising:
a feedback path [Vo] configured to sense the output voltage of the electronic circuit;
an error amplifier [616, 618] component configured to determine a voltage difference [VCOMP] between (i) the output voltage fed to the error amplifier component by the feedback path, and (ii) a reference voltage [Vref]; and
a loop compensation network [R3, C2,C3] configured to cause generation of a voltage compensation signal [output from C3,C2,R3] based on the voltage difference determined by the error amplifier component; and
a second loop [604,608] configured to accelerate the stabilization of an output voltage[Vo] when the transient voltage conditions is being compensated for by the first loop, the second loop comprising:
a transition sensor module [604; Fig. 8, 604, RS, 800 detect Vo ] configured to detect a voltage transient in an output voltage [Io/Vo] of the first loop; and
an amplification module [620,608, paragraph 0021, QR changes duty cycle of PWM signal or level of amp output VCOMP; para 0004] configured to generate a regulation-based-adjustment signal [QR] based on an output signal [VIOS] from the transition sensor module.
With respect to claims 2 and 14, figures 6-8 of Chang et al discloses the electronic system of claim 1, further comprising:
a pulse width modulation (PWM) generation module [612,614]; and
a power stage [610] configured to receive a PWM signal [PWM] from the PWM generation module.
With respect to claims 3 and 15, figures 6-8 of Chang et al discloses the electronic system of claim 2, wherein the regulation-based-adjustment signal is used to drive the PWM generation module. [para 0004,0021; the quick response signal QR will signal the controller 606 to perform a quick transient response, during which the duty cycle or the switching frequency of the control signal PWM will change]
With respect to claims 4 and 16, figures 6-8 of Chang et al discloses the electronic system of claim 3, wherein: the first loop is configured to, in accordance with a determination that the output voltage level fed to the error amplifier component has changed [change in VCOMP], adjusting the PWM from the PWM generation module [changes 612 input level], and the second loop realizes the regulation-based-adjustment signal based on the change in the output voltage. [Para 0021]
With respect to claims 5 and 17, figures 6-8 of Chang et al discloses the electronic system of claim 3, wherein: in accordance with a first determination that the transition sensor module detects an adjustment to the output voltage via the first loop, but does not detecting any voltage level adjustment in the output voltage: [Vios does not cross VQR]
forgoing generating the regulation-based-adjustment signal to drive the PWM generation module, and in accordance with a second determination that the transition sensor module does not detect any adjustment to the output voltage level, but does detect a voltage transient value in the output voltage: [Vios does reach VQR]
generating the regulation-based-adjustment signal [QR] to drive the PWM generation module. [604, 608 is for transient detection. Para 0021]
With respect to claim 6 and 18, figures 6-8 of Chang et al discloses the electronic system of claim 1, wherein the plurality of voltage regulation loops is implemented as a transistor-level design. [M1/M2]
With respect to claim 7 and 19, figures 6-8 of Chang et al discloses the electronic system of claim 1, further comprising: an LC filter [L,C of 610] configured to (i) receive a high-current PWM signal from a power stage and (ii) generate a DC voltage [Vo] by filtering the high-current PWM signal.
With respect to claim 8, figures 6-8 of Chang et al discloses the electronic system of claim 1, wherein the regulation-based-adjustment signal bypasses the loop compensation network. [QR does not interact with R3, C3, C2]
Insofar as understood With respect to claim 9, figures 6-8 of Chang et al discloses the electronic system of claim 1, wherein the first loop further includes a dedicated output component [Chang fig. 6, Vo; applicants specification cites 506 of fig. 5] configured to transmit a voltage reference signal [Vref] configured to provide a setpoint for a voltage regulator control scheme [controls regulator output voltage].
With respect to claim 10, figures 6-8 of Chang et al discloses the electronic system of claim 1, wherein the loop compensation network is part of the error amplifier component. [R3, C3,C2 are connected to input and output of error amp 616]
With respect to claim 20, figures 6-8 of Chang et al. disclose a method of stabilizing an output voltage [Vo], comprising:
at a PMIC including (i) a first loop [606,610] comprising a feedback path [Vo], an error amplifier component [616, 618], and a loop compensation component [R3,C3,C2], and (ii) a second loop [608.604] that includes a transition sensor module [604] and an amplification module [608; paragraph 0021, QR changes duty cycle of PWM signal or level of VCOMP; OR paragraph 0004; therefore providing amplification modification in 608]:
sensing, via the feedback path, the output voltage of an electronic circuit in electronic communication with the PMIC;
determining, via the error amplifier component, a voltage difference [VCOMP] between the output voltage fed to the error amplifier component by the feedback path, and a reference voltage [Vref];
causing generation of a voltage compensation signal [signal from R3, C2, C3] based on the voltage difference [ VCOMP] determined by the error amplifier component; and
after generating the voltage compensation signal:
detecting a voltage transient [604, Fig. 8; 604] in an/the output voltage of the first loop the output voltage of the first loop; and
generating a regulation-based-adjustment signal [QR] based on an output signal from the transition sensor module [VISO].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. 20090001952 in view of Zou et al. 20220247314.
With respect to claim 12, figures 6-8 of Chang et al discloses the electronic system of claim 1, wherein the plurality of voltage regulation loops [616, 618, C2,C3,R3 and 604, 608] is configured to control the output voltage of a respective voltage regulator cell [600].
Chang et al does not disclose “a respective voltage regulator cell of an array of voltage regulator cells.”
However, figures 4A and 6 of Zou et al. discloses voltage regulator cells collectively coupled in a parallel array to provide rail voltage.
It would have been obvious to one skilled in the art before the effective filing date to provide an array of the voltage regulators of Chang et al to select a subset of voltage regulators to collectively provide a respective rail and current since it was known technique in the art.
Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. 20090001952.
With respect to claim 11, figures 6-8 of Chang et al discloses the electronic system of claim 1, but does not disclose wherein the second loop is physically nested within a portion of the first loop.
However, It would have been obvious to one skilled in the art before the effective filing date to nest the second loop 604, 608 inside the first loop, since it has been held that rearranging parts of in invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6-8, 10-12, 13-16, 18, 19 and 20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-15 and 16 of copending Application No. 18/919,345 in view of Chang et al. 2009/0001952.
Claims 1 and 13 and 20 are disclosed by claims 13-15 in view of claim 16 of 18/919345 disclose a complete voltage regulator with first and second feedback loops except for the loop compensation network. Chang et al. discloses voltage regulator with a first and second feedback loops including a loop compensation network [C2, C3, R3] across the error amplifier, see fig. 6 of Chang et al. It would have been obvious to one skilled in the art before the effective filing date to add compensation network to the error amplifier of application 18/919345 as it’s the closest art and a known technique in the art.
Claim 20 is a method claim of claims 1 and 13 in the current application and as such is obvious in view of claims 13-16 of 18/919345 and figure 6 of Chang et al.
Claims 2 and 14 are disclosed by claims 13-16 in view of Chang et al. specifically 13 and 16 of 18/919,345.
Claims 3 and 15 are disclosed by claim 13-16 in view of Chang et al. specifically claim 15 of 18/919,345.
Claims 4 and 16 are disclosed by claims 13-16 of 18/919,345. Claims 4 and 16 describe the function of a voltage regulator with feedback loops.
Claims 6 and 18 are disclose by claims 13-16 and Chang et al. Chang et al. disclose transistor level design in the power stage 602. Applicant specification cites in regard to a transistor level design, for example power stage 518 includes one or mor power field effect transistors.
Claims 7 and 19 are disclosed by claims 13-16 in view of Chang et al. Fig. 6 of Chang et al discloses the LC filter on the output of a power stage.
Claim 8 is disclosed by claims 13-16 in view of Chang et al. Specifically claim 15 discloses the output of the amplification and modulation module adjusts a pulse width of the periodic signal
Claim 10 is disclosed by claims 13-16 in view of Chang et al. Chang et al. discloses the compensation network C2, C3, R3 across input and output of error amplifier 616.
Claim 11 is disclosed by claims 13-16 in view of Chang et al. and In re Japikse, 86 USPQ 70 as seen in claim 11 above.
Claim 12 is disclosed by claims 1, 13-16 in view of Chang et al. Specifically claim 1, “an array of voltage regulator cells, … each voltage regulator set is configured to output a respective rail voltage”
This is a provisional nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached 8:30 - 5:30 PM.
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/Ryan Jager/Primary Examiner, Art Unit 2836 5/2/26
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