Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 5th, 2026 has been entered. Claims 1-8 are pending in this application. Applicant amended independent claim 1 has been amended to further specify that accessing the at least one register is performed through the SPI bus without using a chip bus of the chip under test.
Applicant’s amendments to the claims have been fully considered, however the amendments has necessitated modification of the prior art rejections previously set forth in the Office action mailed March 26th, 2026. Claims 1-8 are rejected under 35 USC § 103, as set forth below.
Response to Arguments
Applicant's arguments filed June 5th, 2026 have been fully considered but they are not persuasive.
Applicant argues that the previously cited references fail to teach or suggest accessing a register through an SPI bus without using a chip bus of the chip under test, and that Wan et al. (US 2023/0376408), hereinafter Wan, fails to teach SPI-based hardware verification. The rejection has been modified to further rely on Guo (US 11,392,533) for the dedicated register/control access architecture distinct from an internal bus. Wan is relied upon for parameter-based test case generation, rather than for the SPI register access features.
Accordingly, Applicant‘s arguments do not overcome the rejection set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 2022/0358270), hereinafter Shen, in view of Wan, and further in view of Guo (US 11,392,533).
Regarding claim 1, Shen teaches a chip verification method based on SPI (Shen, Fig. 1-Fig. 3, para. [0002]-[0004] teaches verification of chip registers and different access manners; para. [0036] teaches that direct access uses an external DUT interface and specifically mentions SPI as one of the communication protocols), comprising the following steps:
(a) obtaining parameter information of a module of a chip under test and a corresponding register within the module (Shen, Fig. 3, S302; para. [0021] teaches register database 231 storing register addresses and detailed attribute parameters; para. [0026] teaches obtaining the corresponding address subject and attribute parameter from the database);
(c) driving the parameter information in the test case onto an SPI bus at a top level of the chip under test through a driver (Shen, para. [0018]-[0019] teaches the top layer, virtual interface, sequences, and driver modules converting sequences into agent signals from the DUT; para. [0028] teaches the driver modules transmitting agent signals to the DUT through the register model or virtual interface), accessing at least one register of a current module of the chip under test, and obtaining an access result (Shen, para. [0027] teaches that the driver modules call the corresponding access modules to perform operations such as read, write, or read/write, on registers 210A-210M), wherein accessing the at least one register is performed through the SPI bus (Shen, para. [0036] & [0041] teaches direct access means directly accessing DUT registers using the external DUT interface, including SPI; it also teaches that specifically for SPI direct access, the SPI direct module is called and operations are performed on registers 210A-210M);
(d) verifying the access result to determine whether a current register of the current module is normal (Shen, para. [0033], lines 1-4, “The comparison module 242 compares the operation records stored in the expectation module 240 and the data signals stored in the fact module 241 to outputs a verification result”);
(e) repeating steps (b) to (d) until all registers of the current module have been verified (Shen teaches multiple registers and repeated operations so repeating steps (b) to (d) is implied); and
(f) repeating steps (a) to (e) until all modules of the chip have been verified (Shen teaches multiple agent modules so repeating steps (a) to (e) is implied).
Shen fails to teach (b) writing a test case for the module based on the parameter information and in step (c), the accessing of the at least one register being performed through the SPI bus without using a chip bus of the chip under test.
However, Wan, in an analogous art, teaches (b) writing a test case for the module based on the parameter information (Wan, Fig. 3, Fig. 4E, & Fig. 5; para. [0014]-[0017] teaches parameter constraint dictionary records/API parameter values or ranges being used in generating a test case set; Fig. 4E teaches a method of generating a test case and determining parameter data instances when generating the test case).
Shen and Wan are both considered to be analogous to the claimed invention because both are in the same field of performing operations on components of an electronic system for testing and/or verification purposes.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the verification method of Shen to incorporate the teachings of Wan by including the functionality of writing test cases for modules based on parameter information.
The suggestion/motivation for doing so would to allow for efficient verification of the device under test, by generating test cases based on specific test parameters.
The combination of Shen in view of Wan, taken singly or combined, fails to teach in step (c), the accessing of the at least one register being performed through the SPI bus without using a chip bus of the chip under test.
However, Guo, in an analogous art, teaches in step (c), the accessing of the at least one register being performed through the SPI bus without using a chip bus of the chip under test (Guo, Figs. 3-4 and Fig. 9, col. 9-10 teach a control bus 304, which may use an SPI protocol, and separately identifies internal bus 306, stating that internal bus 306 is different from control bus 304; Fig. 9, col. 19-20 teaches that register access 440 handles backdoor access to the SPI masters and access to an internal register of the SPI client, as well as teaches that the register access can process single-access requests and backdoor access to both the SPI client and SPI masters).
Shen, Wan, and Guo are considered to be analogous to the claimed invention because they are in the same field of performing operations on components of an electronic system for testing and/or verification purposes.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shen in view of Wan to incorporate the teachings of Guo by including the functionality of providing a dedicated register access path that is different from the internal bus.
The suggestion/motivation for doing so would be to allow for direct access to internal registers for control and diagnostic purposes.
Claims 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Wan, as applied to claim 1 above, and further in view of Kou et al. (CN 118295605) (English translation relied upon), hereinafter Kou.
Regarding claim 2, the combination of Shen in view of Wan, further in view of Guo teaches the chip verification method based on SPI as claimed in claim 1, but fails to teach further comprising setting whether there is an SPI flash device connected in the chip under test within the test case.
The combination of Shen in view of Wan, taken singly or combined, fails to teach further comprising setting whether there is an SPI flash device connected in the chip under test within the test case.
However, Kou, in an analogous art, teaches further comprising setting whether there is an SPI flash device connected in the chip under test within the test case (Kou, Abstract, lines 1-6, “The application provides an SPI Flash back door read-write operation system, method and computer device, setting two channels for accessing external SPI Flash chip: an SPI controller channel and a system bus channel, one of the system bus channel and the SPI controller channel is used for writing data to the sector address designated by the SPI Flash chip, the other one reads data from the sector address designated by the SPI Flash chip”).
Shen, Wan, Guo and Kou are considered to be analogous to the claimed invention because they are in the same field of performing operations on components of an electronic system for testing and/or verification purposes.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shen in view of Wan, further in view of Guo to incorporate the teachings of Hou by including the functionality of a setting that determines whether an SPI flash device is connected in the chip within the test case.
The suggestion/motivation for doing so would be to provide for testing and verification of data transfers between an SPI controller and an SPI flash device to verify the reliability of SPI operations.
Regarding claim 3, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 2, when an SPI flash device is connected in the chip under test, loading data information from the SPI flash into the registers of the current module of the chip under test by configuring an SPI master register within the chip under test (Kou, Abstract, lines 1-6, “The application provides an SPI Flash back door read-write operation system, method and computer device, setting two channels for accessing external SPI Flash chip: an SPI controller channel and a system bus channel, one of the system bus channel and the SPI controller channel is used for writing data to the sector address designated by the SPI Flash chip, the other one reads data from the sector address designated by the SPI Flash chip”). Kou teaches performing read and write operations to an SPI flash via an SPI interface. These operations inherently require some sort of master controller; therefore, it would have been obvious to utilize registers associated with the SPI master to load or control access to SPI flash information.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shen in view of Wan, further in view of Guo to incorporate the teachings of Hou by including the functionality of utilizing an SPI master and registers associated with the master.
The suggestion/motivation for doing so would be that controlling SPI communicate through registers is a conventional technique that allows for configurable access to external memory devices.
Regarding claim 4, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 3, wherein said accessing the at least one register of the current module of the chip under test (Shen teaches register access) in step (c) specifically comprises accessing the data information of the SPI flash loaded onto the registers (Kou, Abstract, lines 1-6). Kou teaches read operations from an SPI flash chip, specifically via backdoor access, which equates to direct retrieval of stored data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shen in view of Wan, further in view of Guo to incorporate the teachings of Hou by including the functionality of loading data retrieved from SPI flash into registers for access during the verification step.
The suggestion/motivation for doing so would be that register-based access provides an efficient interface for processing and comparing data within the verification method.
Regarding claim 5, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 2, wherein when no SPI flash device is connected in the chip under test, said accessing the at least one register of the current module of the chip under test in step (c) specifically comprises accessing original data in the registers. Shen teaches a register database and accessing data in the registers without the presence of a SPI flash device.
Regarding claim 6, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 4, wherein said accessing the at least one register of the current module of the chip under test in step (c) specifically comprises reading data from the registers, writing data to the registers, and reading back the data written (Shen, para. [0016], lines 9-11, “The DUT circuit 21 includes a plurality of registers 210A-210M. The registers 210A to 210M are configured to provide memory functions, such as read and/or write functions”).
Regarding claim 7, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 6, wherein step (d) specifically comprises: comparing the data obtained from the registers with original to determine consistency; and comparing the data written to the registers with the data read from the registers to determine consistency data (Shen, para. [0032], lines 1-2, “The fact module 241 stores the data from the registers 210A-210M of the DUT circuit 21”; para. [0033], lines 1-4, “The comparison module 242 compares the operation records stored in the expectation module 240 and the data signals stored in the fact module 241 to outputs a verification result”).
Regarding claim 8, the combination of Shen in view of Wan, further in view of Guo, and further in view of Kou, teaches the chip verification method based on SPI as claimed in claim 1, wherein the parameter information comprises chip select instructions of the module and address information of the registers (Shen, Fig. 3, S302, “Obtain, according to the received address code, an address subject and an attribute parameter corresponding to the received address code from a register database, and output the corresponding attribute parameter”). While Hou does not explicitly teach chip select instructions, it teaches the use of SPI flash device, therefore it would have been obvious to include chip select instructions when accessing SPI flash because these instructions are inherent in SPI communication.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Shen in view of Wan, further in view of Guo to incorporate the teachings of Hou by including the functionality of including chip select instructions in the parameter information.
The suggestion/motivation for doing so would be that chip select instructions are necessary components of SPI communication used to specify memory locations during data transfer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Krause et al. (US 11,216,407) teaches an SPI master/slave interface used for register access, including read/write commands and address-based access to registers of a slave device.
Li et al. (US 2011/0246708) teaches a multi-channel SPI interface memory controller, separate data paths, and configuration read/write registers used to access internal memory parameters.
Santee et al. (US 10,467,007) teaches SPI cores, internal registers, an on-chip bus, and accessing SPI core resources.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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