DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on October 17, 2025 has been fully considered by the examiner.
Specification
3. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it recites “is described” in lines 1-2 and 6, and “are described” in line 5, which can be implied. Examiner also believes the acronym “SE” in line 3 may be a typographical error as it appears nowhere else in the specification.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Low-Power Static Random Access Memory for At-Memory Compute Architectures.”
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 2-14 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitations “one side of processing element (PE)” in line 2, “an opposite side of processing element (PE)” in line 3, and “the opposite side of processing element (PE)” in line 4, which are indefinite as antecedent basis for “processing element (PE)” has been established in claim 1, lines 1-2.
For the purpose of this action, claim 4 shall be interpreted as “The SRAM of claim 2, further comprising a read main amp (RMA) and latch disposed at every column on one side of the processing element (PE), and data lines (din/dinb) input to the bit line (BL) from an opposite side of the processing element (PE), and wherein the cell vdd selector is disposed at every column at the opposite side of the processing element (PE).” Claims 12-14 depend on claim 4.
Claims 2-3 and 6-7 each recite the limitation “during write operations,” which is indefinite as antecedent basis has already been established for “write operations” in claim 1, line 6. For the purpose of this action, “during write operations” in the aforementioned claims shall be interpreted as “during the write operations.” Claims 3-14 and 18-20 depend on claim 2.
Claims 2-3, 6-7, 12, and 19 each recite the limitation “during read operations,” which is indefinite as antecedent basis has already been established for “read operations” in claim 1, line 7. For the purpose of this action, “during read operations” in the aforementioned claims shall be interpreted as “during the read operations.” Claims 3-14 and 18-20 depend on claim 2.
Claim 5 recites the limitation “the precharge voltage” in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the precharge voltage” in line 4 shall be interpreted as “the bit line (BL) precharge voltage,” for which antecedent basis has been established in claim 2. Claims 6-8 and 18-20 depend on claim 5.
Claim 6 recites the limitation “the two bit line (BL) portions” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the two bit line (BL) portions” shall be interpreted as “the two bit line (BL) segments,” which finds antecedent basis in claim 5. Claims 7-8 and 18-20 depend on claim 6.
Claim 8 recites the limitation “the word line signal” in lines 1 and 4. It is unclear if “the word line signal” refers to “a two-step word line signal” in claim 7, lines 1-2, “a single step word line signal” in claim 7, lines 3-4, or another instance of a word line signal. For the purpose of this action, “the word line signal” shall be interpreted as “the single step word line signal” as the claim appears to be describing a read operation.
Claim 9 recites the limitation “the word line (WL) driver” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the word line (WL) driver” shall be interpreted as “[[the]] a word line (WL) driver.” Claims 10-11 depend on claim 9.
Claim 10 recites the limitation “incorporating the SRAM and processing element (PE)” in lines 2-3, which is indefinite as antecedent basis for “processing element (PE)” has been established in claim 1, lines 1-2. For the purpose of this action, “incorporating the SRAM and processing element (PE)” in lines 2-3 shall be interpreted as “incorporating the SRAM and the processing element (PE).” Claim 11 depends on claim 10.
Claim 10 recites the limitation, “the output of each PT sensor” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the output of each PT sensor” shall be interpreted as “[[the]] an output of each PT sensor.” Claim 11 depends on claim 10.
Claims 12 and 14 each recite the limitation “the isolation (ISO) switch.” There is insufficient antecedent basis for this limitation in the claims. For the purpose of this action, “the isolation (ISO) switch” in claim 12 shall be interpreted as “[[the]] an isolation (ISO) switch,” which shall provide antecedent basis for “the isolation (ISO) switch” in claim 14. Claims 13-14 depends on claim 12.
Claims 12 and 14 each recite the limitation “the far end segment.” There is insufficient antecedent basis for this limitation in the claims. For the purpose of this action, “the far end segment” in claim 12 shall be interpreted as “[[the]] a far end segment,” which shall provide antecedent basis for “the far end segment” in claim 14. Claims 13-14 depends on claim 12.
Claim 14 recites the limitation “the near end segment” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the near end segment” shall be interpreted as “[[the]] a near end segment.”
Claim 17 recites the limitation “the bit line pair” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the bit line pair” shall be interpreted as “[[the]] a bit line pair.”
Claim 18 recites the limitation “the amplitude of the ISO signal for partitioning the bit lines (BL)” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the amplitude of the ISO signal for partitioning the bit lines (BL)” shall be interpreted as “[[the]] an amplitude of the ISO signal for partitioning the bit lines (BL).”
Claim 18 recites the limitation “being the second step word line voltage” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. It is also unclear what “being the second step word line voltage” refers to. That is, it appears from the sentence structure that a word is missing prior to “being,” such that Examiner would expect the following: “voltage_name being [[the]] a second step word line voltage.”
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Snelgrove (US 20180253639 A1) in view of Arimilli, et al (US 20190138079 A1), hereinafter Arimilli, and further in view of Lien, et al (US 6205049 B1), hereinafter Lien.
Regarding independent claim 1, Snelgrove teaches a static random access memory (SRAM) (¶[0014]) embedded in an at-memory architecture (the present application teaches in ¶[0004] “an at-memory compute architecture has the processing elements (PEs) directly attached to the memory cells,” and in ¶[0006] “at-memory compute architecture AI chips where the SRAM is located on-chip adjacent to the processing element,” which is consistent with Snelgrove FIGS. 2 and 13, in which processing elements (PE) 116 are adjacent to and directly connected to memory cells 104 through bit lines 120; ¶[0058]).
Snelgrove does not teach a processing element (PE) operating at a processing element (PE) domain voltage vddp, comprising:
a bit cell operating at a bit cell voltage vdd; and
a cell vdd selector for generating the bit cell voltage at the PE domain voltage (vdd =vddp) during write operations and generating the bit cell voltage at a standard cell voltage (vdd=vddc) during read operations, where the PE domain voltage is less than the standard cell voltage (vddp << vddc).
Arimilli teaches a processing element (PE) operating at a processing element (PE) domain voltage vddp (¶[0007] teaches “an application processor core (APC) voltage supply,” which may be used “to provide the plurality of memories with an APC voltage”),
a bit cell operating at a bit cell voltage vdd (¶[0007] teaches “a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage”); and
a cell vdd selector (¶[0007] teaches “a voltage switching circuit configured to detect an operating mode of the central processing circuit or CPU and switch a voltage provided to at least one of the first group of memory devices or the second group of memory devices between the MX voltage and the APC voltage based on a type of the operating mode detected”).
Arimilli does not teach the operating modes are write and read operating modes.
Lien teaches in the Abstract a “cell voltage control circuit supplies the SRAM cell with the V.sub.CC supply voltage if the SRAM cell is not being written (i.e., during a read mode or a standby mode)” and “If the SRAM cell is being written, the cell voltage control circuit supplies the SRAM cell with a cell voltage that is less than the V.sub.CC supply voltage.”
Therefore, Snelgrove as modified by Arimilli and Lien teaches a static random access memory (SRAM) embedded in an at-memory architecture (Snelgrove) with a processing element (PE) operating at a processing element (PE) domain voltage vddp (Arimilli), comprising:
a bit cell operating at a bit cell voltage vdd (Arimilli, Lien); and
a cell vdd selector (Arimilli, Lien) for generating the bit cell voltage at the PE domain voltage (vdd =vddp) (Arimilli) during write operations (Lien) and generating the bit cell voltage at a standard cell voltage (vdd=vddc) (Arimilli, Lien) during read operations (Lien), where the PE domain voltage is less than the standard cell voltage (vddp << vddc) (Lien).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Arimilli into the method of Snelgrove to include an Array Power Multiplexer (FIG. 5, 508; ¶[0010]). The ordinary artisan would have been motivated to modify Snelgrove in the above manner for the purpose of switching a voltage provided to at least one of the first group of memory devices or the second group of memory devices between the MX (standard memory) voltage and the APC (application processor core) voltage based on a type of the operating mode detected (Arimilli, ¶[0007]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lien into the method of Snelgrove to include switching to an SRAM cell voltage during write mode that is less than an SRAM cell voltage during read mode. The ordinary artisan would have been motivated to modify Snelgrove in the above manner for the purpose of weakening pull-down transistors in the SRAM cell, thereby enabling logic high values to be written to the SRAM cell (Lien, Abstract).
9. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Snelgrove (US 20180253639 A1) in view of Arimilli, et al (US 20190138079 A1), hereinafter Arimilli, further in view of Lien, et al (US 6205049 B1), hereinafter Lien, and further in view of Clinton (US 20190295656 A1).
Regarding claim 15, Snelgrove as modified by Arimilli and Lien teaches the limitations of claim 1.
Snelgrove further teaches the SRAM comprises a top array and a bottom array, but does not teach the top array and the bottom array controlled by independently assigned signals (FIG. 3 shows two banks of memory, but sharing column buses 204, and so are not “independent” as illustrated in FIG. 3I of the present application).
Clinton teaches the SRAM comprises a top array and a bottom array (FIG. 1, 105a, 105b), the top array and the bottom array controlled by independently assigned signals (FIGS. 1, 7, and 11 together show the top and bottom arrays controlled by different bit lines, word lines, and IO blocks).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Clinton into the method of Snelgrove to include independently-controlled top and bottom memory arrays. The ordinary artisan would have been motivated to modify Snelgrove in the above manner for the purpose of improving performance via the shortened bit lines (Clinton ¶[0044]).
10. Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Snelgrove (US 20180253639 A1) in view of Arimilli, et al (US 20190138079 A1), hereinafter Arimilli, further in view of Lien, et al (US 6205049 B1), hereinafter Lien, and further in view of Jang (US 20220084590 A1).
Regarding claim 16, Snelgrove as modified by Arimilli and Lien teaches the limitations of claim 1.
Snelgrove further teaches a read main amp (RMA) (FIG. 8, Sense Amps; ¶[0072]).
Snelgrove does not teach an activation signal (RMA_EN) of the RMA is activated earlier than a complementary activation signal (RMA_ENB) of the RMA.
Jang teaches an activation signal (RMA_EN) of the RMA is activated earlier than a complementary activation signal (RMA_ENB) of the RMA (In the present application, RMA_ENB controls the “header” transistor of the sense amplifier and RMA_EN controls the “footer” transistor; Jang’s “header” transistor (FIG. 2, P1) is controlled by signal AB and Jang’s “footer” transistor is controlled by signal SAE; Jang FIG. 3 shows signal SAE activates before signal AB).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Jang into the method of Snelgrove to include a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed (Jang ¶[0014]). The ordinary artisan would have been motivated to modify Snelgrove in the above manner for the purpose of reducing or preventing occurrences of read disturbance in the memory device when accessing one memory cell may lead to another memory cell being over-written (Jang ¶[0014]).
Regarding claim 17, Snelgrove as modified by Arimilli, Lien, and Jang teaches the limitations of claim 16.
Jang further teaches the activation signal (RMA_EN) is activated and then the complementary activation signal (RMA_ENB) is activated when a voltage difference between the bit line pair reaches a predefined voltage (FIG. 3 shows signal AB, analogous to RMA_ENB, is activated at a time when a voltage difference between the bit line pair reaches dV).
Allowable Subject Matter
11. Claims 2-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
12. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a bit line (BL) precharge circuit for setting a bit line (BL) precharge voltage to less than half of the PE domain voltage (vddp/2) during read operations. Claims 3-14 and 18-20 depend on claim 2.
Citation of Relevant Art
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ito (US 20010006476 A1) teaches a bit line (BL) precharge circuit (FIG. 3, PC; ¶[0061]) for setting a bit line (BL) precharge voltage to half of the PE domain voltage (vddp/2) (¶[0061]) during write operations (FIGS. 3, 5; ¶[0053]).
Braceras, et al (US 20160365139 A1) teaches different precharge voltages for reads and writes, but neither is Vdd/2 and the read precharge voltage is higher than the write precharge voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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