DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 12/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 12/16/2024. These drawings are review and accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-7’s “a control means” that is “configured to” perform recited operations;
Apparatus claims 8-13’s “a controller” that is “configured to” perform recited operations.
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Avraham et al (US 10,998,041 B1 hereinafter “Avraham”) in view of Shikata et al (US 12,249,381 B2 hereinafter “Shikata”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Avraham, for example in Figs. 1-15, discloses a memory apparatus (see for example in Figs. 1-2, 12), comprising:
memory cells (within non-volatile memory array 206; in Fig. 2 related in Figs. 1, 3-15) each connected to one of a plurality of word lines (e.g., PHYSICAL PAGE; in Fig. 3 related in Figs. 1-2, 4-15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., memory states 404, 502; in Figs. 4-8 related in Figs. 1-3, 7-15); and
a control means (e.g., 204/1202; in Figs. 2, 12 related in Figs. 1, 3-11, 13-15) configured to:
read a subset of the memory cells using only one detect read voltage during a detect read operation (e.g., read scan operation; in Figs. 6-8 related in Figs. 1-5, 9-15) prior to a read operation (e.g., read operation; in Figs. 6-8 related in Figs. 1-5, 9-15), and
read the memory cells using at least one adjusted read level for at least one of the plurality of data states during the read operation (see for example in Figs. 6-8 related in Figs. 1-5, 9-15). Avraham discloses the second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors.
However, Avraham is silent with regard to count a detect bit count of one of the memory cells having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage, the at least one adjusted read level based on the detect bit count.
In the same field of Shikata, for example in Figs. 1-12, discloses to count a detect bit count of one of the memory cells (e.g., can also measure the metadata; in Figs. 4-6 related in Figs. 1-3, 7-12) having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage (e.g., read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a lowest threshold voltage distribution to a highest threshold voltage distribution; in Fig. 6 related in Figs. 1-5, 7-12), the at least one adjusted read level based on the detect bit count (see for example in Fig. 6 related in Figs. 1-5, 7-12).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Avraham such as calibrating non-volatile memory read thresholds (see for example in Figs. 1-15 of Avraham) by incorporating the teaching of Shikata such as faster multi-cell read operation using reverse read calibrations (see for example in Figs. 1-12 of Shikata), for the purpose of controlling the data state metric can be represented by a raw bit error rate (RBER), which is the ratio of the number of erroneous bits to the number of all data bits stored in a certain portion of the memory device (e.g., in a specified data block) (Shikata, see Col. 3, lines 46-50).
The structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, the above Avraham/Shikata, combination discloses wherein the at least one adjusted read level includes a plurality of adjusted read levels, each associated with one of the plurality of data states (see for example in Figs. 6-8 related in Figs. 1-5, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the control means is further configured to: determine the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states (see for example in Figs. 6-8 related in Figs. 1-5, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and perform a plurality of reads on each selected word line for the memory cells targeted for each of a plurality of groupings of ones of the plurality of data states in a read operation using the plurality of adjusted read levels determined (see for example in Figs. 6-8 related in Figs. 1-5, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Avraham/Shikata, combination discloses wherein data stored in the memory cells is stored as a plurality of bits in a plurality of pages (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), the plurality of groupings of ones of the plurality of data states includes the plurality of pages (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the control means is further configured to: determine the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states of each of the plurality of pages (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and perform reads on each of the plurality of word lines for the memory cells targeted for each of the plurality of data states in the read operation using the plurality of adjusted read levels determined (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Avraham/Shikata, combination discloses wherein the control means is further configured to: define a linear correlation of read level offsets versus the detect bit count for each of the plurality of data states (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determine the plurality of adjusted read levels using the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by performing the detect read operation (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Avraham/Shikata, combination discloses wherein the plurality of word lines comprise each of a plurality of tiers and the control means is further configured to perform the detect read operation on the memory cells of one of the plurality of tiers and use the plurality of adjusted read levels when reading the memory cells of all of the plurality of tiers (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Avraham/Shikata, combination discloses wherein a slope and an intercept for a linear correlation of real level offsets versus the detect bit count is predetermined for each of the plurality of data states and the control means is further configured to determine the plurality of adjusted read levels using the slope (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above) and the intercept for the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by performing the detect read operation (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Avraham/Shikata, combination discloses wherein the plurality of word lines are grouped into a plurality of word line zones, the subset of the memory cells includes the memory cells of one of the plurality of word lines (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the control means is further configured to: perform the detect read operation for the memory cells connected to one of the plurality of word lines and targeted for one of the plurality of data states (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determine the plurality of adjusted read levels using a plurality of predetermined shifts based on which of the plurality of word line zones the memory cells being read belong, each of the plurality of predetermined shifts corresponding to one of the plurality of word line zones for the one of the plurality of data states (see for example in Figs. 3-8 related in Figs. 1-2, 9-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 8, Avraham, for example in Figs. 1-15, discloses a controller (e.g., CONTROLLER 102; in Figs. 1-2, 12 related in Figs. 3-11, 13-15) in communication with a memory apparatus (e.g., memory 104; in Figs. 1-2, 12 related in Figs. 3-11, 13-15) including memory cells (within memory array 206; in Figs. 2, 12 related in Figs. 1, 3-11, 13-15) each connected to one of a plurality of word lines (e.g., physical page; in Fig. 3 related in Figs. 1-2, 4-15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (see for example in Figs. 4-8, 11 related in Figs. 1-3, 9-10, 12-15), the controller configured to:
instruct the memory apparatus to read a subset of the memory cells using only one detect read voltage (e.g., read scan operation; in Figs. 6-8 related in Figs. 1-5, 9-15) during a detect read operation prior to a read operation (e.g., read operation; in Figs. 6-8 related in Figs. 1-5, 9-15); and
instruct the memory apparatus to read the memory cells using at least one adjusted read level for at least one of the plurality of data states during the read operation (see for example in Figs. 6-8 related in Figs. 1-5, 9-15). Avraham discloses the second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors.
However, Avraham is silent with regard to count a detect bit count of one of the memory cells having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage, the at least one adjusted read level based on the detect bit count.
In the same field of Shikata, for example in Figs. 1-12, discloses to count a detect bit count of one of the memory cells (e.g., can also measure the metadata; in Figs. 4-6 related in Figs. 1-3, 7-12) having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage (e.g., read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a lowest threshold voltage distribution to a highest threshold voltage distribution; in Fig. 6 related in Figs. 1-5, 7-12), the at least one adjusted read level based on the detect bit count (see for example in Fig. 6 related in Figs. 1-5, 7-12).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Avraham such as calibrating non-volatile memory read thresholds (see for example in Figs. 1-15 of Avraham) by incorporating the teaching of Shikata such as faster multi-cell read operation using reverse read calibrations (see for example in Figs. 1-12 of Shikata), for the purpose of controlling the data state metric can be represented by a raw bit error rate (RBER), which is the ratio of the number of erroneous bits to the number of all data bits stored in a certain portion of the memory device (e.g., in a specified data block) (Shikata, see Col. 3, lines 46-50).
The structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 9, the above Avraham/Shikata, combination discloses wherein the at least one adjusted read level includes a plurality of adjusted read levels, each associated with one of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the controller is further configured to: instruct the memory apparatus to determine the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and instruct the memory apparatus to perform a plurality of reads on each selected word line for the memory cells targeted for each of a plurality of groupings of ones of the plurality of data states in a read operation using the plurality of adjusted read levels determined (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, the above Avraham/Shikata, combination discloses wherein data stored in the memory cells is stored as a plurality of bits in a plurality of pages , the plurality of groupings of ones of the plurality of data states includes the plurality of pages (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the controller is further configured to: instruct the memory apparatus to determine the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states of each of the plurality of pages (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and instruct the memory apparatus to perform reads on each of the plurality of word lines for the memory cells targeted for each of the plurality of data states in the read operation using the plurality of adjusted read levels determined (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, the above Avraham/Shikata, combination discloses wherein the controller is further configured to: define a linear correlation of read level offsets versus the detect bit count for each of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determine the plurality of adjusted read levels using the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by performing the detect read operation (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Avraham/Shikata, combination discloses wherein a slope and an intercept for a linear correlation of real level offsets versus the detect bit count is predetermined for each of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above) and the controller is further configured to determine the plurality of adjusted read levels using the slope and the intercept for the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by instructing the memory apparatus to perform the detect read operation (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, the above Avraham/Shikata, combination discloses wherein the plurality of word lines are grouped into a plurality of word line zones, the subset of the memory cells includes the memory cells of one of the plurality of word lines (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the controller is further configured to: instruct the memory apparatus to perform the detect read operation for the memory cells connected to one of the plurality of word lines and targeted for one of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determine the plurality of adjusted read levels using a plurality of predetermined shifts based on which of the plurality of word line zones the memory cells being read belong, each of the plurality of predetermined shifts corresponding to one of the plurality of word line zones for the one of the plurality of data states (see for example in Figs. 3-8, 11 related in Figs. 1-2, 9-10, 12-15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above). Also, the structure in of the prior art (Avraham and Shikata) is substantially identical to the structure of the claims. MPEP 21120.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 14, Avraham, for example in Figs. 1-15, discloses a method of operating a memory apparatus (e.g., memory 104; in Figs. 1-2, 12-14 related in Figs. 3-11, 15) including memory cells (within non-volatile memory array 206; in Fig. 2 related in Figs. 1, 3-15) each connected to one of a plurality of word lines (e.g., PHYSICAL PAGE; in Fig. 3 related in Figs. 1-2, 4-15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., memory states 404, 502; in Figs. 4-8 related in Figs. 1-3, 7-15), the method comprising the steps of:
reading a subset of the memory cells using only one detect read voltage during a detect read operation (e.g., read scan operation; in Figs. 6-8, 14 related in Figs. 1-5, 9-13, 15) prior to a read operation (e.g., read operation; in Figs. 6-8, 14 related in Figs. 1-5, 9-13, 15); and
reading the memory cells using at least one adjusted read level for at least one of the plurality of data states during the read operation (see for example in Figs. 6-8 related in Figs. 1-5, 9-15). Avraham discloses the second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors.
However, Avraham is silent with regard to and counting a detect bit count of one of the memory cells having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage, the at least one adjusted read level based on the detect bit count.
In the same field of Shikata, for example in Figs. 1-12, discloses to count a detect bit count of one of the memory cells (e.g., can also measure the metadata; in Figs. 4-6 related in Figs. 1-3, 7-12) having the threshold voltage above the detect read voltage and the memory cells having the threshold voltage below the detect read voltage (e.g., read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a lowest threshold voltage distribution to a highest threshold voltage distribution; in Fig. 6 related in Figs. 1-5, 7-12), the at least one adjusted read level based on the detect bit count (see for example in Fig. 6 related in Figs. 1-5, 7-12).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Avraham such as calibrating non-volatile memory read thresholds (see for example in Figs. 1-15 of Avraham) by incorporating the teaching of Shikata such as faster multi-cell read operation using reverse read calibrations (see for example in Figs. 1-12 of Shikata), for the purpose of controlling the data state metric can be represented by a raw bit error rate (RBER), which is the ratio of the number of erroneous bits to the number of all data bits stored in a certain portion of the memory device (e.g., in a specified data block) (Shikata, see Col. 3, lines 46-50).
Regarding claim 15, the above Avraham/Shikata, combination discloses wherein the at least one adjusted read level includes a plurality of adjusted read levels, each associated with one of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the method further includes the steps of: determining the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and performing a plurality of reads on each selected word line for the memory cells targeted for each of a plurality of groupings of ones of the plurality of data states in a read operation using the plurality of adjusted read levels determined (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Regarding claim 16, the above Avraham/Shikata, combination discloses wherein data stored in the memory cells is stored as a plurality of bits in a plurality of pages, the plurality of groupings of ones of the plurality of data states includes the plurality of pages (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the method further includes the steps of: determining the plurality of adjusted read levels by performing the detect read operation for the memory cells targeted for one of the plurality of data states of each of the plurality of pages (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and performing reads on each of the plurality of word lines for the memory cells targeted for each of the plurality of data states in the read operation using the plurality of adjusted read levels determined (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Regarding claim 17, the above Avraham/Shikata, combination discloses wherein the method further includes the steps of: defining a linear correlation of read level offsets versus the detect bit count for each of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determining the plurality of adjusted read levels using the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by performing the detect read operation (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Regarding claim 18, the above Avraham/Shikata, combination discloses wherein the plurality of word lines comprise each of a plurality of tiers and the method further includes the step of performing the detect read operation on the memory cells of one of the plurality of tiers and using the plurality of adjusted read levels when reading the memory cells of all of the plurality of tiers (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Regarding claim 19, the above Avraham/Shikata, combination discloses wherein a slope and an intercept for a linear correlation of real level offsets versus the detect bit count is predetermined for each of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above) and the method further includes the step of determining the plurality of adjusted read levels using the slope and the intercept for the linear correlation of the read level offsets versus the detect bit count for each of the plurality of data states based on the detect bit count determined by performing the detect read operation (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Regarding claim 20, the above Avraham/Shikata, combination discloses wherein the plurality of word lines are grouped into a plurality of word line zones, the subset of the memory cells includes the memory cells of one of the plurality of word lines (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above), and the method further includes the steps of: performing the detect read operation for the memory cells connected to one of the plurality of word lines and targeted for one of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above); and determining the plurality of adjusted read levels using a plurality of predetermined shifts based on which of the plurality of word line zones the memory cells being read belong, each of the plurality of predetermined shifts corresponding to one of the plurality of word line zones for the one of the plurality of data states (see for example in Figs. 3-8, 11, 14 related in Figs. 1-2, 9-10, 12-13, 15 of Avraham and also see in Figs. 4-6 related in Figs. 1-3, 7-12 of Shikata, as discussed above).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 07/02/2026
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