DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on December 16, 2024 has been fully considered by the examiner.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “the memory cells form a block including a first sub-block vertically below a second sub-block” in lines 4-5. However, the antecedent for “the memory cells” in this limitation is “memory cells each connected to one of a plurality of word lines” in line 2. It is unclear how memory cells connected to one word line can form multiple vertical sub-blocks.
For the purpose of this action, lines 2-5 shall be interpreted as: “memory cells forming a block including a first sub-block vertically below a second sub-block, each memory cell connected to one of a plurality of word lines and disposed in memory holes extending vertically through a stack of the plurality of word lines.” Claims 2-7 depend on claim 1.
Claim 1 recites the limitation, “the memory cells being programmed in a program operation” in lines 8-9. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cells being programmed in a program operation” shall be interpreted as “[[the]] memory cells being programmed in a program operation.”
Claim 1 recites the limitation, “the plurality of word lines of the second sub-block” in line 13. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the plurality of word lines of the second sub-block” shall be interpreted as “[[the]] a plurality of word lines of the second sub-block.”
Claims 1-5, 7-11, 13-18, and 20 each recite the limitation, “plurality of word lines,” often with no clarifying qualifiers. Some cases appear to refer to word lines throughout a block (e.g., claim 1, lines 2-4; claim 4, line 1). Some cases contextually appear likely to refer to word lines in the second sub-block (e.g., claim 2, lines 8-10). Some cases are ambiguous (e.g., claim 5, in which “plurality of word lines” in line 2 appears intentionally distinguished from “plurality of word lines of the second sub-block” in lines 8-9, but also refers to claim 2, lines 8-10, which seems to be in the context of the second sub-block).
Claim 2 recites the limitation, “wherein the memory cells are configured” in lines 1-2. It is unclear if “the memory cells” refer to “memory cells each connected to one of a plurality of word lines” in claim 1, lines 2-3 (i.e., memory cells in a specific word line), “memory cells form a block” in claim 1, line 4 (i.e., any memory cell in a block), or “memory cells being programmed” in claim 1, lines 8-9.
For the purpose of this action, “wherein the memory cells are configured” shall be interpreted as “wherein the memory cells being programmed are configured” as seemingly implied by the idea of retaining threshold voltages. Claims 3-7 depend on claim 2.
Claim 4 recites the limitation, “the memory cells are connected in series” in line 3. It is unclear if “the memory cells” refer to “memory cells each connected to one of a plurality of word lines” in claim 1, lines 2-3 (i.e., memory cells in a specific word line), “memory cells form a block” in claim 1, line 4 (i.e., any memory cell in a block), or “memory cells being programmed” in claim 1, lines 8-9.
For the purpose of this action, “the memory cells are connected in series” shall be interpreted as “the memory cells that form a block are connected in series” as the context discusses the overall structure of the memory apparatus.
Claim 5 recites the limitations “an select gate program voltage” in line 4, and “a select gate program voltage” in line 7, the latter being indefinite. For the purpose of this action, the aforementioned limitations shall be interpreted as “[[an]] a select gate program voltage” in line 4, and “[[a]] the select gate program voltage” in line 7. Claims 6-7 depend on claim 5.
Claim 7 recites the limitations, “the memory cells connected to the unselected ones of the plurality of word lines” in lines 3-4 and “the memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation” in lines 4-6. There is insufficient antecedent basis for these limitations in the claim.
For the purpose of this action, lines 3-6 shall be interpreted as: “[[the]] memory cells connected to the unselected ones of the plurality of word lines while reducing adverse boosting effects on [[the]] memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation.”
Claim 8 recites the limitation, “the memory cells form a block including a first sub-block vertically below a second sub-block” in lines 3-4. However, the antecedent for “the memory cells” in this limitation is “memory cells each connected to one of a plurality of word lines” in lines 1-2. It is unclear how memory cells connected to one word line can form multiple vertical sub-blocks.
For the purpose of this action, lines 1-4 shall be interpreted as: “memory cells forming a block including a first sub-block vertically below a second sub-block, each memory cell connected to one of a plurality of word lines and disposed in memory holes extending vertically through a stack of the plurality of word lines.” Claims 9-13 depend on claim 8.
Claim 8 recites the limitation, “the memory cells being programmed in a program operation” in lines 7-8. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cells being programmed in a program operation” shall be interpreted as “[[the]] memory cells being programmed in a program operation.”
Claim 9 recites the limitation, “wherein the memory cells are configured” in line 1. It is unclear if “the memory cells” refer to “memory cells each connected to one of a plurality of word lines” in claim 8, lines 1-2 (i.e., memory cells in a specific word line), “memory cells form a block” in claim 8, lines 3-4 (i.e., any memory cell in a block), or “memory cells being programmed” in claim 8, lines 7-8.
For the purpose of this action, “wherein the memory cells are configured” shall be interpreted as “wherein the memory cells being programmed are configured” as seemingly implied by the idea of retaining threshold voltages. Claims 10-13 depend on claim 9.
Claim 11 recites the limitations “an select gate program voltage” in line 4, and “a select gate program voltage” in line 6, the latter being indefinite. For the purpose of this action, the aforementioned limitations shall be interpreted as “[[an]] a select gate program voltage” in line 4, and “[[a]] the select gate program voltage” in line 6. Claims 12-13 depend on claim 11.
Claim 13 recites the limitations, “the memory cells connected to the unselected ones of the plurality of word lines” in lines 3-4 and “the memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation” in lines 4-6. There is insufficient antecedent basis for these limitations in the claim.
For the purpose of this action, lines 3-6 shall be interpreted as: “[[the]] memory cells connected to the unselected ones of the plurality of word lines while reducing adverse boosting effects on [[the]] memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation.”
Claim 14 recites the limitation, “the memory cells form a block including a first sub-block vertically below a second sub-block” in lines 3-4. However, the antecedent for “the memory cells” in this limitation is “memory cells each connected to one of a plurality of word lines” in lines 1-2. It is unclear how memory cells connected to one word line can form multiple vertical sub-blocks.
For the purpose of this action, lines 1-4 shall be interpreted as: “memory cells forming a block including a first sub-block vertically below a second sub-block, each memory cell connected to one of a plurality of word lines and disposed in memory holes extending vertically through a stack of the plurality of word lines.” Claims 15-20 depend on claim 14.
Claim 14 recites the limitation, “the memory cells being programmed in a program operation” in lines 7-8. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cells being programmed in a program operation” shall be interpreted as “[[the]] memory cells being programmed in a program operation.”
Claim 15 recites the limitation, “wherein the memory cells are configured” in line 1. It is unclear if “the memory cells” refer to “memory cells each connected to one of a plurality of word lines” in claim 14, lines 1-2 (i.e., memory cells in a specific word line), “memory cells form a block” in claim 14, lines 3-4 (i.e., any memory cell in a block), or “memory cells being programmed” in claim 14, line 7.
For the purpose of this action, “wherein the memory cells are configured” shall be interpreted as “wherein the memory cells being programmed are configured” as seemingly implied by the idea of retaining threshold voltages. Claims 16-20 depend on claim 15.
Claim 17 recites the limitation, “the memory cells are connected in series” in line 3. It is unclear if “the memory cells” refer to “memory cells each connected to one of a plurality of word lines” in claim 14, lines 1-2 (i.e., memory cells in a specific word line), “memory cells form a block” in claim 14, lines 3-4 (i.e., any memory cell in a block), or “memory cells being programmed” in claim 14, line 7.
For the purpose of this action, “the memory cells are connected in series” shall be interpreted as “the memory cells that form a block are connected in series” as the context discusses the overall structure of the memory apparatus.
Claim 18 recites the limitations “an select gate program voltage” in line 4, and “a select gate program voltage” in line 6, the latter being indefinite. For the purpose of this action, the aforementioned limitations shall be interpreted as “[[an]] a select gate program voltage” in line 4, and “[[a]] the select gate program voltage” in line 6. Claims 19-20 depend on claim 18.
Claim 20 recites the limitations, “the memory cells connected to the unselected ones of the plurality of word lines” in lines 3-4 and “the memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation” in lines 4-6. There is insufficient antecedent basis for these limitations in the claim.
For the purpose of this action, lines 3-6 shall be interpreted as: “[[the]] memory cells connected to the unselected ones of the plurality of word lines while reducing adverse boosting effects on [[the]] memory cells connected to ones of the plurality of the word lines adjacent the at least one edge word line during the program operation.”
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-3, 8-10, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo (US 20180233207 A1).
Regarding independent claim 1, Seo teaches a memory apparatus (FIGS. 1 and 2, 1110), comprising:
memory cells (FIG.6, e.g., C0..Cn) each connected to one of a plurality of word lines (FIG. 6, e.g., WL0..WLn) and disposed in memory holes extending vertically through a stack of the plurality of word lines (FIGS. 3, 8; ¶[0061]), the memory cells form a block (FIG. 2, MB1..MBk) including a first sub-block (FIG. 8, e.g., stack STA_1; ¶[0096]) vertically below a second sub-block (FIG. 8, STA_2); and
a control means (FIG. 2, Control Logic 300, Peripheral Circuit 200; ¶[0044]) configured to:
determine a vertical location in the second sub-block of a selected one of the plurality of word lines connected to the memory cells being programmed in a program operation (FIG. 9, groups RG2_1..RG2_k; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”), and
apply at least one programming pulse of a program voltage to the selected one of the plurality of word lines to program the memory cells connected thereto (FIG. 4, S44, S47) while applying ones of a plurality of pass voltages (FIG. 9, Vpass1, Vpass2) to unselected ones of the plurality of word lines of the second sub-block during the program operation (FIG. 4, S43, S44), the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the vertical location of the selected one of the plurality of word lines (FIG. 9; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding independent claim 8, Seo teaches a controller (FIG. 1, 1120) in communication with a memory apparatus (FIGS. 1 and 2, 1110) including memory cells (FIG.6, e.g., C0..Cn) each connected to one of a plurality of word lines (FIG. 6, e.g., WL0..WLn) and disposed in memory holes extending vertically through a stack of the plurality of word lines (FIGS. 3, 8; ¶[0061]), the memory cells form a block (FIG. 2, MB1..MBk) including a first sub-block (FIG. 8, e.g., stack STA_1; ¶[0096]) vertically below a second sub-block (FIG. 8, STA_2), the controller configured to (¶[0039], [0041], [0044]):
determine a vertical location in the second sub-block of a selected one of the plurality of word lines connected to the memory cells being programmed in a program operation (FIG. 9, groups RG2_1..RG2_k; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
instruct the memory apparatus to apply at least one programming pulse of a program voltage to the selected one of the plurality of word lines to program the memory cells connected thereto (FIG. 4, S44, S47) while applying ones of a plurality of pass voltages (FIG. 9, Vpass1, Vpass2) to unselected ones of the plurality of word lines of the second sub-block during the program operation (FIG. 4, S43, S44), the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the vertical location of the selected one of the plurality of word lines (FIG. 9; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding independent claim 14, Seo teaches a method of operating a memory apparatus (FIG. 4) including memory cells (FIG.6, e.g., C0..Cn) each connected to one of a plurality of word lines (FIG. 6, e.g., WL0..WLn) and disposed in memory holes extending vertically through a stack of the plurality of word lines (FIGS. 3, 8; ¶[0061]), the memory cells form a block (FIG. 2, MB1..MBk) including a first sub-block (FIG. 8, e.g., stack STA_1; ¶[0096]) vertically below a second sub-block (FIG. 8, STA_2), the method comprising the steps of:
determining a vertical location in the second sub-block of a selected one of the plurality of word lines connected to the memory cells being programmed in a program operation (FIG. 9, groups RG2_1..RG2_k; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
applying at least one programming pulse of a program voltage to the selected one of the plurality of word lines to program the memory cells connected thereto (FIG. 4, S44, S47) while applying ones of a plurality of pass voltages (FIG. 9, Vpass1, Vpass2) to unselected ones of the plurality of word lines of the second sub-block during the program operation (FIG. 4, S43, S44), the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the vertical location of the selected one of the plurality of word lines (FIG. 9; ¶[0099] teaches “a program pass voltage may be adjusted depending on the location of the selected word line”; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 2, Seo teaches the limitations of claim 1.
Seo further teaches the memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states (¶[0046] teaches “a program voltage apply operation for applying a program voltage to a selected word line coupled to the selected page, and a program verify operation for determining whether threshold voltages of memory cells coupled to the selected word line have reached target levels”; FIG. 4), the plurality of word lines of the second sub-block (FIG. 8, STA_2) include at least one edge word line disposed vertically above all other ones of the plurality of word lines of the second sub-block (WL15 is shown disposed vertically above WL8..WL14), and the control means further configured to:
determine a proximity of the selected one of the plurality of word lines to the at least one edge word line (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
select the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the proximity of the selected one of the plurality of word lines to the at least one edge word line (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 3, Seo teaches the limitations of claim 2.
Seo further teaches the second sub-block includes an edge word line border comprising a predetermined border quantity (¶[0066] teaches “Before the program operation is performed, each cell string may be divided into a plurality of pillar regions…”) of the plurality of word lines of the second sub-block adjacent the at least one edge word line, and the control means is further configured to:
determine whether the selected one of the plurality of word lines is within the edge word line border (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
select the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines differently in response to the selected one of the plurality of word lines being within the edge word line border as compared to the selected one of the plurality of word lines not being within the edge word line border (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 9, Seo teaches the limitations of claim 8.
Seo further teaches the memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states (¶[0046] teaches “a program voltage apply operation for applying a program voltage to a selected word line coupled to the selected page, and a program verify operation for determining whether threshold voltages of memory cells coupled to the selected word line have reached target levels”; FIG. 4), the plurality of word lines of the second sub-block (FIG. 8, STA_2) include at least one edge word line disposed vertically above all other ones of the plurality of word lines of the second sub-block (WL15 is shown disposed vertically above WL8..WL14), and the controller further configured to:
determine a proximity of the selected one of the plurality of word lines to the at least one edge word line (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
select the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the proximity of the selected one of the plurality of word lines to the at least one edge word line (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 10, Seo teaches the limitations of claim 9.
Seo further teaches the second sub-block includes an edge word line border comprising a predetermined border quantity (¶[0066] teaches “Before the program operation is performed, each cell string may be divided into a plurality of pillar regions…”) of the plurality of word lines of the second sub-block adjacent the at least one edge word line, and the controller is further configured to:
determine whether the selected one of the plurality of word lines is within the edge word line border (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
select the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines differently in response to the selected one of the plurality of word lines being within the edge word line border as compared to the selected one of the plurality of word lines not being within the edge word line border (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 15, Seo teaches the limitations of claim 14.
Seo further teaches the memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states (¶[0046] teaches “a program voltage apply operation for applying a program voltage to a selected word line coupled to the selected page, and a program verify operation for determining whether threshold voltages of memory cells coupled to the selected word line have reached target levels”; FIG. 4), the plurality of word lines of the second sub-block (FIG. 8, STA_2) include at least one edge word line disposed vertically above all other ones of the plurality of word lines of the second sub-block (WL15 is shown disposed vertically above WL8..WL14), and the method further includes the steps of:
determining a proximity of the selected one of the plurality of word lines to the at least one edge word line (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
selecting the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines based on the proximity of the selected one of the plurality of word lines to the at least one edge word line (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Regarding claim 16, Seo teaches the limitations of claim 15.
Seo further teaches the second sub-block includes an edge word line border comprising a predetermined border quantity (¶[0066] teaches “Before the program operation is performed, each cell string may be divided into a plurality of pillar regions…”) of the plurality of word lines of the second sub-block adjacent the at least one edge word line, and the method further includes the steps of:
determining whether the selected one of the plurality of word lines is within the edge word line border (FIG. 9, see region RGn_k; ¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…”); and
selecting the one of the plurality of pass voltages used for each of the unselected ones of the plurality of word lines differently in response to the selected one of the plurality of word lines being within the edge word line border as compared to the selected one of the plurality of word lines not being within the edge word line border (¶[0104] teaches “When the selected word line is included in the kth pillar region RGn_k that is located in an uppermost portion…a first pass voltage Vpass1 may be applied to the unselected word lines except for the selected word line” and “When the selected word line is included in the first pillar region RGn_1 that is located in a lowermost portion…a second pass voltage Vpass2 higher than the first pass voltage Vpass1 may be applied to unselected word lines adjacent to the top of or the top and bottom of the selected word line…”).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20180233207 A1) in view of Wang, et al (US 20230386580 A1), hereinafter Wang.
Regarding claim 4, Seo teaches the limitations of claim 3.
Seo further teaches the plurality of word lines (FIGS. 8-9, WL0..WLn) extend horizontally (FIGS. 3 and 8, x-direction), the memory cells are connected in series (see FIG. 9) between at least one drain-side select gate transistor (FIGS. 8-9, DST coupled to DSL) on a drain-side of each of the memory holes (¶[0061]) and at least one source-side select gate transistor (FIGS. 8-9, SST coupled to SSL) on a source-side of each of the memory holes (FIGS. 8-9, SST coupled to SSL is at the SL end of the memory hole) the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines (FIGS. 8-9, DST coupled to DSL is shown coupled to BL) and the at least one source-side select gate transistor of each of the memory holes is coupled to a source line (FIGS. 8-9, SST coupled to SSL is shown coupled to SL), and the at least one edge word line includes a plurality of edge word lines (FIGS. 8-9, e.g., WL7, WL15, WLn).
Seo does not explicitly teach a plurality of dielectric layers and the word lines and dielectric layers overlay one another in an alternating fashion in the stack. However, Seo teaches in ¶[0059] a BiCS structure.
Wang teaches in ¶[0004] a BiCS architecture “comprises a stack of alternating conductive and dielectric layers.”
Therefore, in teaching a BiCS structure, Seo further teaches the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack.
Regarding claim 17, Seo teaches the limitations of claim 16.
Seo further teaches the plurality of word lines (FIGS. 8-9, WL0..WLn) extend horizontally (FIGS. 3 and 8, x-direction), the memory cells are connected in series (see FIG. 9) between at least one drain-side select gate transistor (FIGS. 8-9, DST coupled to DSL) on a drain-side of each of the memory holes (¶[0061]) and at least one source-side select gate transistor (FIGS. 8-9, SST coupled to SSL) on a source-side of each of the memory holes (FIGS. 8-9, SST coupled to SSL is at the SL end of the memory hole), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines (FIGS. 8-9, DST coupled to DSL is shown coupled to BL) and the at least one source-side select gate transistor of each of the memory holes is coupled to a source line (FIGS. 8-9, SST coupled to SSL is shown coupled to SL), and the at least one edge word line includes a plurality of edge word lines (FIGS. 8-9, e.g., WL7, WL15, WLn).
Seo does not explicitly teach a plurality of dielectric layers and the word lines and dielectric layers overlay one another in an alternating fashion in the stack. However, Seo teaches in ¶[0059] a BiCS structure.
Wang teaches in ¶[0004] a BiCS architecture “comprises a stack of alternating conductive and dielectric layers.”
Therefore, in teaching a BiCS structure, Seo further teaches the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack.
Allowable Subject Matter
9. Claims 5-7, 11-13, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the plurality of pass voltages applied to the unselected ones of the plurality of word lines while applying the at least one programming pulse of the program voltage to the selected one of the plurality of word lines includes an select gate program voltage applied to the at least one edge word line and a first pass voltage and a second pass voltage, and the control means is further configured to:
apply a select gate program voltage to the at least one edge word line while applying the second pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically above the selected one of the plurality of word lines in the stack other than the at least one edge word line and while applying the first pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically below the selected one of the plurality of word lines in the stack in response to the selected one of the plurality of word lines not being within the edge word line border. Claims 6-7 depend on claim 5.
Regarding claim 11, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the plurality of pass voltages applied to the unselected ones of the plurality of word lines while applying the at least one programming pulse of the program voltage to the selected one of the plurality of word lines includes an select gate program voltage applied to the at least one edge word line and a first pass voltage and a second pass voltage, and the controller is further configured to:
instruct the memory apparatus to apply a select gate program voltage to the at least one edge word line while applying the second pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically above the selected one of the plurality of word lines in the stack other than the at least one edge word line and while applying the first pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically below the selected one of the plurality of word lines in the stack in response to the selected one of the plurality of word lines not being within the edge word line border. Claims 12-13 depend on claim 11.
Regarding claim 18, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the plurality of pass voltages applied to the unselected ones of the plurality of word lines while applying the at least one programming pulse of the program voltage to the selected one of the plurality of word lines includes an select gate program voltage applied to the at least one edge word line and a first pass voltage and a second pass voltage, and the method further includes the steps of:
applying a select gate program voltage to the at least one edge word line while applying the second pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically above the selected one of the plurality of word lines in the stack other than the at least one edge word line and while applying the first pass voltage to the unselected ones of the plurality of word lines of the second sub-block disposed vertically below the selected one of the plurality of word lines in the stack in response to the selected one of the plurality of word lines not being within the edge word line border. Claims 19-20 depend on claim 18.
Citation of Relevant Art
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cui, et al (US 20250046376 A1) teaches in FIG. 8A different pass voltages applied to word lines above and below a word line selected for programming, which may include the case in which a “second” pass voltage is applied to an edge word line while a “first” pass voltage is applied to other unselected word lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights