Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US Pub # 2024/0161831) in view of Dutta et al. (US Pub # 2014/0119126).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Jung et al. teach a memory device, comprising: one or more components configured to: receive, from a host device, a program command instructing the memory device to write host data to a memory; and program the host data to the memory using a program scheme associated with multiple programming pulses (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131 where program command CMD received by the controller unit 140 and writing operation done by unit 130) including: permitting, during a first programming pulse, of the multiple programming pulses, a memory cell to receive a first program voltage; inhibiting, during a second programming pulse, of the multiple programming pulses, the memory cell from receiving a second program voltage; and inhibiting, during a third programming pulse, of the multiple programming pulses, the memory cell from receiving a third program voltage (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, Program pulses Vpgm1…Vpgm7, Verify voltages Vvf1…Vvf4); verify the program scheme using a majority vote program verify scheme, including: performing, following the first programming pulse, a first program verify procedure for the memory cell; performing, following the second programming pulse, a second program verify procedure for the memory cell; performing, following the third programming pulse, a third program verify procedure for the memory cell; and determining whether the memory cell passes a majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, second program state P2 start if first program state P1 is partially passed, partially means higher than preset first value (see specially paragraph 0097) indicate majority condition); and perform one of: inhibiting, during a fourth programming pulse, of the multiple programming pulses, the memory cell from receiving a fourth program voltage when the memory cell passes the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure, or permitting, during the fourth programming pulse, the memory cell to receive the fourth program voltage when the memory cell does not pass the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, fourth program pulse Vpgm4 would be applied even if majority of Vvf1….Vvf3 does not pass but second program state partially passed).
Jung et al. teach external device coupled to memory controller 140 to receive CMD command (see paragraph 0035) but are silent about host device.
Dutta et al. teach host device (see Fig.1, paragraph 0048, controller 140 coupled to host device through 120 link).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dutta et al. to the teaching of Jung et al. where external device of Jung et al. would be replaced with host device taught by Dutta et al. in order to send required command to controller and to improve accuracy of program operation (see Dutta et al, paragraph 0123).
Further reason to combine the teachings of Dutta et al. and Jung et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards programming and verification operation of memory array.
Regarding dependent claims 2, Jung et al. further teach wherein the one or more components are further configured to: determine that the memory cell passes the first program verify procedure; and inhibit the memory cell from receiving the second program voltage based on determining that the memory cell passes the first program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107).
Regarding dependent claims 3, Jung et al. further teach wherein the one or more components, to verify the program scheme using the majority vote program verify scheme, are configured to verify only a subset of memory cells associated with the memory using the majority vote program verify scheme, and wherein the memory cell is included in the subset of memory cells (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0110).
Regarding dependent claims 4, Jung et al. further teach wherein the one or more components are further configured to: permit, during the fourth programming pulse, the memory cell to receive the fourth program voltage; and apply, during the fourth programming pulse, a bit line voltage to the memory cell, wherein the bit line voltage corresponds to a sum of a selective slow programming convergence voltage and two times an incremental step pulse programming voltage (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120).
Regarding dependent claims 5, Jung et al. further teach wherein the program scheme is associated with at least one of: an incremental step pulse programming scheme, a drain-to-source program order, a source-to-drain program order, a normal block usage program scheme, a half good block program scheme, or a block by deck program scheme (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095).
Regarding dependent claims 6, Jung et al. further teach wherein the memory cell is associated with one of a triple level cell or a quad level cell (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0111).
Regarding dependent claims 7, Jung et al. further teach wherein the memory device is associated with one of a NAND memory device, a resistive random-access memory device, or a phase-change memory device (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117).
Regarding independent claim 8, Jung et al. teach a method, comprising: receiving, by a memory device from a host device, a program command instructing the memory device to write host data to a memory; programming, by the memory device, the host data to the memory using a program scheme associated with multiple programming pulses (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131 where program command CMD received by the controller unit 140 and writing operation done by unit 130), including: permitting, during a first programming pulse, of the multiple programming pulses, a memory cell to receive a first program voltage; inhibiting, during a second programming pulse, of the multiple programming pulses, the memory cell from receiving a second program voltage; and inhibiting, during a third programming pulse, of the multiple programming pulses, the memory cell from receiving a third program voltage; verifying, by the memory device, the program scheme using a majority vote program verify scheme (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, second program state P2 start if first program state P1 is partially passed, partially means higher than preset first value (see specially paragraph 0097) indicate majority condition), including: performing, following the first programming pulse, a first program verify procedure for the memory cell; performing, following the second programming pulse, a second program verify procedure for the memory cell; performing, following the third programming pulse, a third program verify procedure for the memory cell; and determining whether the memory cell passes a majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, Program pulses Vpgm1…Vpgm7, Verify voltages Vvf1…Vvf4); and performing, by the memory device, one of: inhibiting, during a fourth programming pulse, of the multiple programming pulses, the memory cell from receiving a fourth program voltage when the memory cell passes the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure, or permitting, during the fourth programming pulse, the memory cell to receive the fourth program voltage when the memory cell does not pass the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, fourth program pulse Vpgm4 would be applied even if majority of Vvf1….Vvf3 does not pass but second program state partially passed).
Jung et al. teach external device coupled to memory controller 140 to receive CMD command (see paragraph 0035) but are silent about host device.
Dutta et al. teach host device (see Fig.1, paragraph 0048, controller 140 coupled to host device through 120 link).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dutta et al. to the teaching of Jung et al. where external device of Jung et al. would replaced with host device taught by Dutta et al. in order to send required command to controller and to improve accuracy of program operation (see Dutta et al, paragraph 0123).
Further reason to combine the teachings of Dutta et al. and Jung et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards programming and verification operation of memory array.
Regarding dependent claims 9, Jung et al. further teach the method of claim 8, further comprising: determining, by the memory device, that the memory cell passes the first program verify procedure; and inhibiting, by the memory device, the memory cell from receiving the second program voltage based on determining that the memory cell passes the first program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091).
Regarding dependent claims 10, Jung et al. further teach wherein verifying the program scheme using the majority vote program verify scheme comprises verifying only a subset of memory cells associated with the memory using the majority vote program verify scheme, and wherein the memory cell is included in the subset of memory cells (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107).
Regarding dependent claims 11, Jung et al. further teach wherein the bit line voltage corresponds to a sum of a selective slow programming convergence voltage and two times an incremental step pulse programming voltage (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109).
Regarding dependent claims 12, Jung et al. further teach wherein the program scheme is associated with at least one of: an incremental step pulse programming scheme, a drain-to-source program order, a source-to-drain program order, a normal block usage program scheme, a half good block program scheme, or a block by deck program scheme (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0110).
Regarding dependent claims 13, Jung et al. further teach wherein the memory cell is associated with one of a triple level cell or a quad level cell (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0100).
Regarding dependent claims 14, Jung et al. further teach wherein the memory device is associated with one of a NAND memory device, a resistive random-access memory device, or a phase-change memory device (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107).
Regarding independent claim 15, Jung et al. teach a non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a memory device, cause the memory device to: receive, from a host device, a program command instructing the memory device to write host data to a memory (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131 where program command CMD received by the controller unit 140 and writing operation done by unit 130); and program the host data to the memory using a program scheme associated with multiple programming pulses, including: permitting, during a first programming pulse, of the multiple programming pulses, a memory cell to receive a first program voltage; inhibiting, during a second programming pulse, of the multiple programming pulses, the memory cell from receiving a second program voltage; and inhibiting, during a third programming pulse, of the multiple programming pulses, the memory cell from receiving a third program voltage; verify the program scheme using a majority vote program verify scheme (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, second program state P2 start if first program state P1 is partially passed, partially means higher than preset first value (see specially paragraph 0097) indicate majority condition), including: performing, following the first programming pulse, a first program verify procedure for the memory cell; performing, following the second programming pulse, a second program verify procedure for the memory cell; performing, following the third programming pulse, a third program verify procedure for the memory cell (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131, Program pulses Vpgm1…Vpgm7, Verify voltages Vvf1…Vvf4); and determining whether the memory cell passes a majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure; and perform one of: inhibiting, during a fourth programming pulse, of the multiple programming pulses, the memory cell from receiving a fourth program voltage when the memory cell passes the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure, or permitting, during the fourth programming pulse, the memory cell to receive the fourth program voltage when the memory cell does not pass the majority of the first program verify procedure, the second program verify procedure, and the third program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117, 0120-0131).
Jung et al. teach external device coupled to memory controller 140 to receive CMD command (see paragraph 0035) but are silent about host device.
Dutta et al. teach host device (see Fig.1, paragraph 0048, controller 140 coupled to host device through 120 link).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Dutta et al. to the teaching of Jung et al. where external device of Jung et al. would replaced with host device taught by Dutta et al. in order to send required command to controller and to improve accuracy of program operation (see Dutta et al, paragraph 0123).
Further reason to combine the teachings of Dutta et al. and Jung et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards programming and verification operation of memory array.
Regarding dependent claims 16, Jung et al. further teach wherein the one or more instructions further cause the memory device to: determine that the memory cell passes the first program verify procedure; and inhibit the memory cell from receiving the second program voltage based on determining that the memory cell passes the first program verify procedure (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109).
Regarding dependent claims 17, Jung et al. further teach wherein the one or more instructions, that cause the memory device to verify the program scheme using the majority vote program verify scheme, cause the memory device to verify only a subset of memory cells associated with the memory using the majority vote program verify scheme, and wherein the memory cell is included in the subset of memory cells (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0110).
Regarding dependent claims 18, Jung et al. further teach wherein the one or more instructions further cause the memory device to: permit, during the fourth programming pulse, the memory cell to receive the fourth program voltage; and apply, during the fourth programming pulse, a bit line voltage to the memory cell, wherein the bit line voltage corresponds to a sum of a selective slow programming convergence voltage and two times an incremental step pulse programming voltage (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107, 0109-0117).
Regarding dependent claims 19, Jung et al. further teach wherein the program scheme is associated with at least one of: an incremental step pulse programming scheme, a drain-to-source program order, a source-to-drain program order, a normal block usage program scheme, a half good block program scheme, or a block by deck program scheme (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091, 0095-0107).
Regarding dependent claims 20, Jung et al. further teach wherein the memory cell is associated with one of a triple level cell or a quad level cell (see Fig. 1-4, 6-14, paragraph 0026-0028, 0032-0037, 0047-0055, 0057-0067, 0069-0081, 0083-0091).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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