Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejection
Claim 13 is rejected under 35 U.S.C. §112(b) as being indefinite because the claims fail to particularly point out and distinctly claim the subject matter regarded as the invention.
Claim 13
Issue: Limitations the set of NAND strings is indefinite because the prior limitations identify a first set and a second set. Accordingly, it is unclear which set is intended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Maejima et al. (US Pub # 2024/0096417) in view of Lee (US Pub # 2015/0325306).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Maejima et al. teach an apparatus comprising: a memory structure having a plurality of NAND strings, a plurality of word lines connected to the plurality of NAND strings having memory cells, and a plurality of bit lines associated with the plurality of NAND strings (see Fig. 1-2 and paragraph 0017-0018, 0030, wordline WL0…WLn coupled to NAND strings STR); and one or more control circuits in communication with the memory structure, the one or more control circuits including: a first plurality of sense amplifiers configured to sense memory cells on a first set of the plurality of NAND strings, the first set of NAND strings associated with a first set of bit lines of the plurality of bit lines; and a second plurality of sense amplifiers configured to sense memory cells on a second set of the plurality of NAND strings, the second set of NAND strings associated with a second set of bit lines of the plurality of bit lines (see Fig. 1-2 and paragraph 0017-0018, 0030, sense amp module 5 includes sense amps S/A for each string coupled to bit line BL), wherein the one or more control circuits are configured to: apply a reference voltage to a first set of selected memory cells on the first set of NAND strings and a second set of selected memory cells on the second set of NAND strings while applying a pass voltage to unselected memory cells on the first set of NAND strings and the second set of NAND strings during a sense operation thereby resulting in first currents in the first set of NAND strings and second currents in the second set of NAND strings; and operate the first plurality of sense amplifiers and the second plurality of sense amplifiers to recycle the first currents for use as a current source for the second currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078, 0093-0095, cell current flow is top to bottom (BL to SL) for left portion and bottom to top (SL to BL) for right portion of memory portion 23C, see specially Fig. 12A).
Even though Maejima et al. teach reading / sensing operation but silent exclusively about reference
voltage and applying a pass voltage to unselected memory cells on the first set of NAND strings.
Lee teaches applying reference voltage and applying a pass voltage to unselected memory cells on the
first set of NAND strings (see paragraph 0057, 100, 0123-0124, 0141-0146, reference voltage Vr, Pass
voltage Vpass).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lee to the teaching of Maejima et al. in where reference voltage and pass voltage of Lee would be applied during sensing operation taught by Maejima et al. in order to effectively execute sensing / reading operation and to control unintentional voltage increase of common source line and improve reliability of reading / sensing operation (see Lee, paragraph 0007).
Further reason to combine the teachings of Lee and Maejima et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards sensing operation of memory array.
Regarding dependent claims 2, Maejima et al. further teach wherein the first set of NAND strings and the second set of NAND strings are connected to a common source line to which the first currents sink and from which the second currents are sourced in order to recycle the first currents for use as the current source for the second currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077).
Regarding dependent claims 3, Maejima et al. further teach configured to sense memory cell currents that flow from the first set of bit lines to the common source line; and the second plurality of sense amplifiers are configured to sense memory cell currents that flow from the common source line to the second set of bit lines (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072).
Regarding dependent claims 4, Maejima et al. further teach the apparatus of claim 1, wherein: the first set of NAND strings are connected to a first source line; the second set of NAND strings are connected to a second source line; and the first set of sense amplifiers and the second set of sense amplifiers are connected to a common node to which the first currents flow and from which the second currents are sourced in order to recycle the first currents for use as the current source for the second currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054
Regarding dependent claims 5, Maejima et al. further teach configured to sense memory cell currents that flow from the first source line to the first set of bit lines; and the second plurality of sense amplifiers are configured to sense memory cells currents that flow from the second set of bit lines to the second source line (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078).
Regarding dependent claims 6, Maejima et al. further teach wherein the first currents flow from the first set of NAND strings to first set of sense amplifiers to the second source line and then to second set of NAND strings to in order to recycle the first currents for use as the current source for the second currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0050).
Regarding dependent claims 7, Maejima et al. further teach configured to sense memory cells currents that flow from the first source line to the first set of bit lines; and the second plurality of sense amplifiers are configured to sense memory cells currents that flow from the second source line to the second set of bit lines (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054).
Regarding dependent claims 8, Maejima et al. further teach wherein the first currents flow from the first set of NAND strings to the first source line to the second set of sense amplifiers and then to second set of NAND strings to in order to recycle the first currents for use as the current source for the second currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0049).
Regarding dependent claims 9, Maejima et al. further teach configured to sense memory cells currents that flow from the first set of bit lines to the first source line; and the second plurality of sense amplifiers are configured to sense memory cells currents that flow from the second set of bit lines to the second source line (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072).
Regarding dependent claims 10, Maejima et al. further teach configured to sense memory cells currents that flow from the first set of bit lines to a source line; the second plurality of sense amplifiers are configured to sense memory cells currents that flow from a source line to the second set of bit lines; and the one or more control circuits are configured to: apply a verify reference voltage to a selected word line connected to the first set of selected memory cells and the second set of selected memory cells during a verify operation; and apply a read reference voltage to the selected word line connected to the first set of selected memory cells and the second set of selected memory cells during a read operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078).
Regarding dependent claims 11, Maejima et al. further teach configured to sense memory cells currents that flow from the first set of bit lines to a source line connected to the first set of NAND strings; the second plurality of sense amplifiers are configured to sense memory cells currents that flow from a source line connected to the second set of NAND strings to the second set of bit lines; and the one or more control circuits are configured to: apply the reference voltage to a first selected word line connected to the first set of selected memory cells and a second selected word line connected to the second set of selected memory cells during the sense operation, wherein a first distance from the first selected word line to the source line connected to the first set of NAND strings is substantially equal to a second distance from the second selected word line to the second set of bit lines (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078, 0093).
Regarding independent claim 12, Maejima et al. teach a method for sensing NAND memory cells, the method comprising: applying a reference voltage to a first set of selected NAND memory cells on a first set of NAND strings and a second set of selected NAND memory cells on a second set of NAND strings (see Fig. 1-2 and paragraph 0017-0018, 0030, wordline WL0…WLn coupled to NAND strings STR) while applying a pass voltage to unselected memory cells on the first set of NAND strings and the second set of NAND strings during a sense operation of the first set of selected memory cells and the second set of selected memory cells to thereby result in first NAND string currents of the first set of NAND strings and second NAND string currents of the second set of NAND string; and providing a current pathway between the first set of NAND strings and the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078, 0093-0095, cell current flow is top to bottom (BL to SL) for left portion and bottom to top (SL to BL) for right portion of memory portion 23C, see specially Fig. 12A).
Even though Maejima et al. teach reading / sensing operation but silent exclusively about reference
voltage and applying a pass voltage to unselected memory cells on the first set of NAND strings.
Lee teaches applying reference voltage and applying a pass voltage to unselected memory cells on the
first set of NAND strings (see paragraph 0057, 100, 0123-0124, 0141-0146, reference voltage Vr, Pass
voltage Vpass).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lee to the teaching of Maejima et al. in where reference voltage and pass voltage of Lee would be applied during sensing operation taught by Maejima et al. in order to effectively execute sensing / reading operation and to control unintentional voltage increase of common source line and improve reliability of reading / sensing operation (see Lee, paragraph 0007).
Further reason to combine the teachings of Lee and Maejima et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards sensing operation of memory array.
Regarding dependent claims 13, Maejima et al. further teach wherein providing the current pathway between the first set of NAND strings and the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation comprises: controlling a first set of sense amplifiers associated with the first set of NAND strings and a second set of sense amplifiers associated with the second set of NAND strings to route the first NAND string currents through a common source line connected to the first set of NAND strings and the set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078).
Regarding dependent claims 14, Maejima et al. further teach wherein providing the current pathway between the first set of NAND strings and the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation comprises: controlling a first set of sense amplifiers associated with the first set of NAND strings and a second set of sense amplifiers associated with the second set of NAND strings to route the first NAND string currents through the first set of sense amplifiers to the second set of sense amplifiers such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072).
Regarding dependent claims 15, Maejima et al. further teach wherein providing the current pathway between the first set of NAND strings and the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation comprises: controlling a first set of sense amplifiers associated with the first set of NAND strings and a second set of sense amplifiers associated with the second set of NAND strings to route the first NAND string currents through the first set of sense amplifiers to a source line connected to the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078, 0093).
Regarding dependent claims 16, Maejima et al. further teach wherein providing the current pathway between the first set of NAND strings and the second set of NAND strings such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation comprises: controlling a first set of sense amplifiers associated with the first set of NAND strings and a second set of sense amplifiers associated with the second set of NAND strings to route the first NAND string currents to a source line connected to the first set of NAND strings to the second set of sense amplifiers such that the first NAND string currents serve as a source of current for the second NAND string currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078).
Regarding independent claim 17, Maejima et al. teach a non-volatile storage system, comprising: a memory structure having a plurality of NAND strings, a plurality of word lines connected to the plurality of NAND strings, and a plurality of bit lines associated with the plurality of NAND strings (see Fig. 1-2 and paragraph 0017-0018, 0030, wordline WL0…WLn coupled to NAND strings STR); and one or more control circuits in communication with the memory structure, the one or more control circuits including: a first plurality of sense amplifiers configured to sense memory cells on a first set of the plurality of NAND strings, the first set of NAND strings associated with a first set of bit lines of the plurality of bit lines; and a second plurality of sense amplifiers configured to sense memory cells on a second set of the plurality of NAND strings, the second set of NAND strings associated with a second set of bit lines of the plurality of bit lines (see Fig. 1-2 and paragraph 0017-0018, 0030, sense amp module 5 includes sense amps S/A for each string coupled to bit line BL), wherein the one or more control circuits are configured to: control the first plurality of sense amplifiers to charge the first set of bit lines with first bit line charging currents during a sense operation of selected memory cells on the first set of NAND strings; and control the second plurality of sense amplifiers to charge the second set of bit lines with second bit line charging currents during the sense operation of selected memory cells on the second set of NAND strings, including recycle the first bit line charging currents for use as a current source for the second bit line charging currents during the sense operation (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054, 0067-0072, 0077-0078, 0093-0095, cell current flow is top to bottom (BL to SL) for left portion and bottom to top (SL to BL) for right portion of memory portion 23C, see specially Fig. 12A).
Even though Maejima et al. teach reading / sensing operation but silent exclusively about reference
voltage and applying a pass voltage to unselected memory cells on the first set of NAND strings.
Lee teaches applying reference voltage and applying a pass voltage to unselected memory cells on the
first set of NAND strings (see paragraph 0057, 100, 0123-0124, 0141-0146, reference voltage Vr, Pass
voltage Vpass).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lee to the teaching of Maejima et al. in where reference voltage and pass voltage of Lee would be applied during sensing operation taught by Maejima et al. in order to effectively execute sensing / reading operation and to control unintentional voltage increase of common source line and improve reliability of reading / sensing operation (see Lee, paragraph 0007).
Further reason to combine the teachings of Lee and Maejima et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards sensing operation of memory array.
Regarding dependent claims 18, Maejima et al. further teach the non-volatile storage system of claim 17, wherein: the first set of NAND strings are connected to a first source line; the second set of NAND strings are connected to a second source line; and the first plurality of sense amplifiers each have a node connected to the second source line (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054).
Regarding dependent claims 19, Maejima et al. further teach the non-volatile storage system of claim 17, wherein: the first plurality of sense amplifiers each have a transistor connected to a common node, the common node sinks the first bit line charging currents; and the second plurality of sense amplifiers each have a transistor connected to the common node, the common node sources the second bit line charging currents (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0050).
Regarding dependent claims 20, Maejima et al. further teach configured to sense memory cell currents that flow from a source line connected to the first set of NAND strings to the first set of bit lines; and the second plurality of sense amplifiers are configured to sense memory cell current that flows from the second set of bit line to a source line connected to the second set of NAND strings (see Fig. 1-3, 5-8, 12 and paragraph 0017-0018, 0030, 0034-0036, 0047-0054).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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