Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 4-5, 10, 13, 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, 20 of U.S. Patent No. 12,169,999. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding pending claim 1, Claim 1 of US 12,169,999 discloses the claimed invention but fails to explicitly teach slots for placement of physical gaming chips, a processor and a first segmented portion and a second portion. However, Claim 1 of US 12,169,999 discloses adjacent columns as slots for placement of physical gaming chips, a tracking control for a processor and an upper and lower portion as the first segmented portion and second portions. Claim 1 of US 12,169,999 also discloses additional limitations of the columns and aligned substantially parallel to a vertical height of the columns. Claim 1 of US 12,169,999 discloses the limitations of pending claim 1 and therefore anticipates pending claim 1.
Claim 1 of US 12,169,999 of discloses the limitations of pending claims 2, 4 and 5 and therefore anticipates pending claims 2, 4 and 5.
Similarly Claim 12 of US 12,169,999 anticipates pending claim 10.
Claim 120 of US 12,169,999 anticipates pending claim 18.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The closest prior art Bulzacki (US 2023/0032920) discloses an apparatus (Figs. 26a, 26c, 32B) comprising:
a chip tray comprising slots for placement of physical gaming chips (2602, 3204 in Figs. 26A, 26C, 32B);
image sensors (2606 in Figs. 26a, 26C) positioned relative to at least one of the slots (For example, First camera 2606a in Figs. 26A is at least between first, second and third chip columns); and
one or more electronic processors configured to execute instructions, which when executed cause the apparatus to perform operations to (102 on Fig 1a; paragraphs 285, 289, 314, 339, 350, 389, 421):
capture, via the image sensors, image data of a chip stack in the at least one of the slots (paragraphs 536, 541-551);
detect, via a machine learning model, a value of each gaming chip in the chip stack in response analysis of chip-edge features of each gaming chip in the chip stack (applies machine learning to recognize and identify chips; paragraphs 278, 282-283); and
electronically present information (paragraphs 273, 304-307, 332-333, 350, 415, 621-631) associated with detection of the value of each gaming chip in the chip stack (paragraphs 270, 295, 326, 326, 329, 350, 564, 567).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jasson H Yoo whose telephone number is (571)272-5563. The examiner can normally be reached M-F 9am-5pm.
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/JASSON H YOO/Primary Examiner, Art Unit 3715
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