DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Regarding [0020]: What exactly is meant by “a higher PV” and “a lower PB”? Does PV mean a program-verify voltage or a loop count?
Regarding [0025]: Change “an addition” to “an additional”.
Regarding [0026, 0052]: What exactly is meant by “RWB”?
Regarding [0064]: Change “satisfy a condition” to “satisfies a condition”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2015/0221374).
Regarding claim 1: Lee teaches a memory device comprising:
a memory array (110 in FIG. 1; [0019]); and
control logic (120 in FIG. 1), operatively coupled with the memory array, to perform operations comprising:
receiving a request (CMD; [0027]) to execute a programming operation to program cells of the memory array to a set of programming levels (each selected memory cell is to be programmed to a target level; [0028,0047, 0062]);
executing a first program verify loop (S303 and S305 in FIG. 3) associated with a programming level of the set of programming levels, wherein executing the first program verify loop comprises causing an initial bitline voltage (0V is observed to be an initial bit line voltage in FIG. 5 and then the bit line voltage is seen to be incremented upon a loop number reaching a reference number) to be applied to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage (a range lower than the target voltage, is understood to mean that the memory cell has a threshold voltage between zero volts and the program verify voltage since the transistors in FIG. 2 are recognized to be n-type; [0046]); and
executing a subsequent program verify loop (a second instance of executing S303 and S305) associated with the programming level (the target level), wherein executing the subsequent program verify loop comprises causing an adjusted bitline voltage to be applied to the subset of the cells (executing the second instance of S303 and S305 causes another adjusted bit line voltage to be applied to the cells in a third instance of executing S303 and S305).
Regarding claim 2: Lee teaches the memory device of claim 1, the control logic is to perform operations further comprising: determining a count value associated with the subsequent program verify loop satisfies a condition; and in response to determining that the condition is satisfied, establishing the adjusted bitline voltage (FIG. 3, FIG. 5 or FIG. 6).
Regarding claim 3: Lee teaches the memory device of claim 1, wherein the adjusted bitline voltage equals the initial bitline voltage increased by a step bitline voltage level (an increment from 0V to a first program permission volage; [0051]; FIG. 5 or FIG. 6).
Regarding claim 4: Lee teaches the memory device of claim 1, the control logic is to perform operations further comprising:
determining a count value associated with a second subsequent program verify loop (a third instance of executing S303 and S305) satisfies a condition; and
in response to determining that the condition is satisfied, establishing a second adjusted bitline voltage (using the alternative of a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 5: Lee teaches the memory device of claim 4, the control logic is to perform operations further comprising: executing the second subsequent program verify loop associated with the programming level, wherein executing the second subsequent program verify loop comprises causing the second adjusted bitline voltage to be applied to the subset of the cells (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065])
Regarding claim 6: Lee teaches The memory device of claim 5, wherein the second adjusted bitline voltage equals the adjusted bitline voltage increased by a step bitline voltage level (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 7: Lee teaches the memory device of claim 1, the control logic is to perform operations further comprising: executing a final program verify loop associated with the programming level, wherein executing the final program verify loop comprises causing a final bitline voltage to be applied to the subset of the cells (see last loop in FIG. 5 or FIG. 6).
Regarding claim 8: Lee teaches a method comprising:
receiving a request (CMD; [0027]) to execute a programming operation to program cells of a memory device to a set of programming levels (each selected memory cell is to be programmed to a target level; [0028,0047, 0062]);
executing a first program verify loop (S303 and S305 in FIG. 3) associated with a programming level of the set of programming levels, wherein executing the first program verify loop comprises causing an initial bitline voltage (0V is observed to be an initial bit line voltage in FIG. 5 and then the bit line voltage is seen to be incremented upon a loop number reaching a reference number) to be applied to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage (a range lower than the target voltage, is understood to mean that the memory cell has a threshold voltage between zero volts and the program verify voltage since the transistors in FIG. 2 are recognized to be n-type; [0046]); and
executing a subsequent program verify loop (a second instance of executing S303 and S305) associated with the programming level (the target level), wherein executing the subsequent program verify loop comprises causing an adjusted bitline voltage to be applied to the subset of the cells (executing the second instance of S303 and S305 causes another adjusted bit line voltage to be applied to the cells in a third instance of executing S303 and S305).
Regarding claim 9: Lee teaches the method further comprising: determining a count value associated with the subsequent program verify loop satisfies a condition; and in response to determining that the condition is satisfied, establishing the adjusted bitline voltage (FIG. 3, FIG. 5 or FIG. 6).
Regarding claim 10: Lee teaches the method, wherein the adjusted bitline voltage equals the initial bitline voltage increased by a step bitline voltage level (an increment from 0V to a first program permission volage; [0051]; FIG. 5 or FIG. 6).
Regarding claim 11: Lee teaches the method, further comprising:
determining a count value associated with a second subsequent program verify loop (a third instance of executing S303 and S305) satisfies a condition; and
in response to determining that the condition is satisfied, establishing a second adjusted bitline voltage (using the alternative of a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 12: Lee teaches the method, further comprising:
executing the second subsequent program verify loop associated with the programming level, wherein executing the second subsequent program verify loop comprises causing the second adjusted bitline voltage to be applied to the subset of the cells (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065])
Regarding claim 13: Lee teaches the method, wherein the second adjusted bitline voltage equals the adjusted bitline voltage increased by a step bitline voltage level (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 14: Lee teaches the method, further comprising:
executing a final program verify loop associated with the programming level, wherein executing the final program verify loop comprises causing a final bitline voltage to be applied to the subset of the cells (see last loop in FIG. 5 or FIG. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (2015/0221374) in view of McNeil (2021/0398599).
Regarding claim 15: Lee ([0027-0028]; 120 of FIG. 1) teaches a control circuit:
receiving a request (CMD input from an external device; [0027]) to execute a programming operation to program cells of a memory device to a set of programming levels (each selected memory cell is to be programmed to a target level; [0028,0047, 0062]);
executing a first program verify loop (S303 and S305 in FIG. 3) associated with a programming level of the set of programming levels, wherein executing the first program verify loop comprises causing an initial bitline voltage (0V is observed to be an initial bit line voltage in FIG. 5 and then the bit line voltage is seen to be incremented upon a loop number reaching a reference number) to be applied to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage (a range lower than the target voltage, is understood to mean that the memory cell has a threshold voltage between zero volts and the program verify voltage since the transistors in FIG. 2 are recognized to be n-type; [0046]); and
executing a subsequent program verify loop (a second instance of executing S303 and S305) associated with the programming level (the target level), wherein executing the subsequent program verify loop comprises causing an adjusted bitline voltage to be applied to the subset of the cells (executing the second instance of S303 and S305 causes another adjusted bit line voltage to be applied to the cells in a third instance of executing S303 and S305).
Lee does not specifically teach a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device would cause the processing device to perform the above steps already being performed by the control circuit.
McNeil (claim 8; 20210398599) teaches A non-transitory machine-readable medium that stores instructions that, when executed by a system, cause the system to perform operations comprising programming and verify operations.
It would have been obvious to one of ordinary skill in the art to incorporate the teaching of McNeil into the device and/or method of Lee in a manner such that a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device would cause the processing device to issue the CMD signal such that he control circuit of Lee would perform the above steps already disclosed by Lee.
Regarding claim 16: Lee teaches the operations further comprising:
determining a count value associated with the subsequent program verify loop satisfies a condition; and
in response to determining that the condition is satisfied, establishing the adjusted bitline voltage (FIG. 3, FIG. 5 or FIG. 6).
Regarding claim 17: Lee teaches the adjusted bitline voltage equals the initial bitline voltage increased by a step bitline voltage level (an increment from 0V to a first program permission volage; [0051]; FIG. 5 or FIG. 6).
Regarding claim 18: Lee teaches the operations, further comprising:
determining a count value associated with a second subsequent program verify loop (a third instance of executing S303 and S305) satisfies a condition; and
in response to determining that the condition is satisfied, establishing a second adjusted bitline voltage (using the alternative of a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 19: Lee teaches the operations, further comprising:
executing the second subsequent program verify loop associated with the programming level, wherein executing the second subsequent program verify loop comprises causing the second adjusted bitline voltage to be applied to the subset of the cells (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]), wherein the second adjusted bitline voltage equals the adjusted bitline voltage increased by a step bitline voltage level (as seen in the alternative using a second program permission voltage as illustrated in FIG. 5 or FIG. 6; [0051; 0065]).
Regarding claim 20: Lee teaches the operations, further comprising:
executing a final program verify loop associated with the programming level, wherein executing the final program verify loop comprises applying a final bitline voltage to the subset of the cells (see last loop in FIG. 5 or FIG. 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights