Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 12/17/2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11/842,893. The instant applications claim similar subject matter as the US Patent No. 11/842,893 with the exceptions of some limitations such as wherein a bottom surface of the cavity has a step are taught by Vinciarelli et al. (US 2008/0112139 A1 of (fig. 17C). For instance:
Regarding claim 1, claims 1 and 1 of U.S. Patent No. 11/842,893 teaches A circuit board (claim 1, line 1) comprising: a base insulating layer (claim 1, line 2); and an upper insulating layer (claim 1, line 3) disposed on the base insulating layer (claim 1, line 2), wherein the upper insulating layer (claim 1, line 5) includes a cavity (claim 1, line 5) passing through at least a portion of the upper insulating layer (claim 1, line 5)
But, U.S. Patent No. 11/842,893 does not explicitly teach wherein a bottom surface of the cavity has a step.
However, Vinciarelli et al. teaches wherein a bottom surface of the cavity (403, 404 see fig. 17C) has a step (417a, 417b, see paragraph [0072], lines 1-15, see fig. 17C).
Therefore, at the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide a upper insulating layer along a vertical direction, and wherein a bottom surface of the cavity has a step in the device of claim 1 of the US Patent No. 11/842, 893 based on the teachings of Vinciarelli et al. in order to embedded recess (cavity) built down into its stack up layers and step at the bottom of the cavity allows the designer to place components of varying thicknesses (such as different profiles of IC chips, capacitors, or sensors) into the same cavity while keeping their top surfaces perfectly flush with the upper insulating layer.
Pertaining to claim 2, claims 6 of U.S. Patent No. 11/842,893 teaches wherein the base insulating layer includes a plurality of insulating layers laminated in the vertical direction (claim 6).
Pertaining to claim 3, claims 5 of U.S. Patent No. 11/842,893 teaches wherein the bottom surface of the cavity is positioned higher than an upper surface of the base insulating layer with respect to a lower surface of the base insulating layer (claim 5).
Allowable Subject Matter
7. Claims 4-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the specific limitations of "wherein the bottom surface of the cavity includes a first portion connected to an inner wall of the cavity, and a second portion connected to the first portion and positioned further from the inner wall than the first portion and having the step with respect to the first portion," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 8-17 depends from claim 7 and is therefore allowed for at the same reasons.
Regarding claim 9, the specific limitations of "wherein an inner wall of the cavity includes a first inner wall corresponding to an inner wall of the through hole, a second inner wall corresponding to an inner wall of the recess, and a contact portion in which the first inner wall and the second inner wall are in contact.," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record.
Regarding claim 18, the specific limitations of "a protective layer disposed on the upper insulating layer, and wherein the protective layer has an opening overlapping the cavity along the vertical direction.," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 19 depends from claim18 and is therefore allowed for at the same reasons.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability should not be negated by the manner in which the invention was made.
9. This application is currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
10. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (KR 2017067472) in view of Vinciarelli et al. (US 2008/0112139 A1).
Pertaining to claim 1, Baek discloses A circuit board (Abstract) comprising: a base insulating layer (10, see fig. 1); and an upper insulating layer (30, see fig. 1) disposed on the base insulating layer (10), wherein the upper insulating layer (30) includes a cavity (C, see fig. 1) passing through at least a portion of the upper insulating layer (30) along a vertical direction (see fig. 1).
But, Baek does not explicitly teach wherein a bottom surface of the cavity has a step.
However, Vinciarelli et al. teaches wherein a bottom surface of the cavity (403, 404, see fig. 17C) has a step (417a, 417b, see fig. 17C and see paragraph [0072], lines 1-15).
Therefore, at the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide a upper insulating layer along a vertical direction, and wherein a bottom surface of the cavity has a step in the device of claim 1 of the US Patent No. 11/842, 893 based on the teachings of Vinciarelli et al. in order to embedded recess (cavity) built down into its stack up layers and step at the bottom of the cavity allows the designer to place components of varying thicknesses (such as different profiles of IC chips, capacitors, or sensors) into the same cavity while keeping their top surfaces perfectly flush with the upper insulating layer.
Pertaining to claim 2, Baek discloses wherein the base insulating layer (10) includes a plurality of insulating layers laminated in the vertical direction (see fig. 1).
Pertaining to claim 3, Baek discloses, wherein the bottom surface of the cavity is positioned higher than an upper surface of the base insulating layer with respect to a lower surface of the base insulating layer (see figs. 1 and 10).
Allowable Subject Matter
11. Claims 4-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the specific limitations of "wherein the bottom surface of the cavity includes a first portion connected to an inner wall of the cavity, and a second portion connected to the first portion and positioned further from the inner wall than the first portion and having the step with respect to the first portion," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 8-17 depends from claim 7 and is therefore allowed for at the same reasons.
Regarding claim 9, the specific limitations of "wherein an inner wall of the cavity includes a first inner wall corresponding to an inner wall of the through hole, a second inner wall corresponding to an inner wall of the recess, and a contact portion in which the first inner wall and the second inner wall are in contact.," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record.
Regarding claim 18, the specific limitations of "a protective layer disposed on the upper insulating layer, and wherein the protective layer has an opening overlapping the cavity along the vertical direction.," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 19 depends from claim 18 and is therefore allowed for at the same reasons.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamaguchi (US-20080296051-A1)
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/ANDARGIE M AYCHILLHUM/Primary Examiner, Art Unit 2848
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