DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 12/17/2024.
Claims 1-20 are pending. Claims 1, 5, and 10 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 12/17/2024, and 03/09/2026. All IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
7. Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No.US 12,211,544 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other. She analysis in the following. In US 12,211,544 B2, generally more specific circuitry component names were used; but layout, orientation, function appears to be the same.
For example: first sense amplifier in US 12,211,544 B2 is same as first circuit in instant application. See analysis of the limitations in the following.
Regarding independent claim 1, US12211544B2 teaches a semiconductor device (US12211544B2: claim 1, line 1. See also claims 1-8) comprising:
a first storage portion; (US12211544B2: claim 1, line 2: “storage portion associated with “first memory cell”)
a first wiring extending in a first direction, the first wiring being electrically coupled to the first storage portion;
(US12211544B2: claim 1, lines 3-4: “…first bit line extending in a first direction… first bit line electrically coupled to the first memory cell…”)
a first circuit configured to sense a voltage of the first wiring; (US12211544B2: claim 1, lines 5-6: “…first sense amplifier configured to sense a voltage of the first bit line…”)
a second storage portion; (US12211544B2: claim 1, line 7: “storage portion associated with “second memory cell”)
a second wiring adjacent to the first wiring and extending in the first direction, the second wiring being electrically coupled to the second storage portion; (US12211544B2: claim 1, lines 8-10: "...second bit line adjacent to the
first bit line and extending in the first direction, the second bit line being electrically coupled to the second memory cell...")
a second circuit configured to sense a voltage of the second wiring; (US12211544B2: claim 1, lines 11-12: “…second sense amplifier configured to sense a voltage of the second bit line…”)
a third storage portion; (US12211544B2: claim 1, line 13: “storage portion associated with “third memory cell”)
a third wiring extending in the first direction, the third wiring being electrically coupled to the third storage portion; (US12211544B2: claim 1, lines 14-16: “… third bit line extending in the first direction and being electrically coupled to the third memory cell…”)
a third circuit configured to sense a voltage of the third wiring; (US12211544B2: claim 1, lines 17-18: “…third sense amplifier configured to sense a voltage of the third bit line…”)
a first pad disposed between the first wiring and the first circuit; (US12211544B2: claim 1, lines 19-20: “…first pad disposed between the first bit line and the first sense amplifier…”)
a second pad disposed between the second wiring and the second circuit; and (US12211544B2: claim 1, lines 21-22: “…second pad disposed between the second bit line and the second sense amplifier…”)
a third pad disposed between the third wiring and the third circuit, (third pad disposed between the third bit line and the third sense amplifier, (US12211544B2: claim 1, lines 23-24: “…third pad disposed between the third bit line and the third sense amplifier…”)
wherein:
the first circuit and the second circuit belong to a first group, are adjacent to each other, and are arranged in a second direction intersecting the first direction, (US12211544B2: claim 1, lines 26-29: “…first sense amplifier and the second sense amplifier belong to a first sense amplifier group, are adjacent to each other, and are arranged in a second direction intersecting to the first direction…”)
the third circuit belongs to a second group (US12211544B2: claim 1, lines 30-31: “…third sense amplifier belongs to a second sense amplifier group…”),
the first group and the second group are adjacent to each other and arranged in the first direction, and (US12211544B2: claim 1, lines 32-34: “…first sense amplifier group and the second sense amplifier group are adjacent to each other and arranged in the first direction…”),
the first pad, the second pad, and the third pad are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction. (US12211544B2: claim 1, lines 35-38: “…first pad, the second pad, and the third pad are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction…”)
Regarding claim 2, US12211544B2 teaches the semiconductor device according to claim 1, further comprising: a first conductive layer; a fourth circuit coupled to the first conductive layer, the fourth circuit being configured to apply a first voltage to the first conductive layer; a second conductive layer; and a fifth circuit coupled to the second conductive layer, the fifth circuit being configured to apply a second voltage to the second conductive layer, wherein the first group is disposed between the fourth circuit and the fifth circuit. (US12211544B2: claim 2, lines 1-13)
Regarding claim 3, US12211544B2 teaches the semiconductor device according to claim 1, further comprising: a first conductive line electrically coupled between the first pad and the first circuit, the first conductive line extending in the second direction; (US12211544B2: claim 3, lines 1-11)
a second conductive line electrically coupled between the second pad and the second circuit, the second conductive line extending in the second direction; and a third conductive line electrically coupled
between the third pad and the third circuit, the third conductive line extending in the second direction.
(US12211544B2: claim 3, lines 1-11)
Regarding claim 4, US12211544B2 teaches the semiconductor device according to claim 3, wherein the second conductive line extends in the second direction over the first circuit.
(US12211544B2: claim 4, lines 1-3)
Regarding independent claim 5, US12211544B2 teaches a semiconductor device (US12211544B2: claim 9, line 1) comprising:
a first storage portion; (US12211544B2: claim 9, line 2: storage portion associated with “first memory cell”)
a first wiring extending in a first direction, the first wiring being electrically coupled to the first storage portion;
(US12211544B2: claim 9, lines 3-4: “…first bit line extending in a first direction, the first bit line being electrically coupled to the first memory cell…”)
a first circuit configured to sense a voltage of the first wiring; (US12211544B2: claim 9, lines 5-6: “…first sense amplifier configured to sense a voltage of the first bit line…”)
a second storage portion; (US12211544B2: claim 9, line 7: storage portion associated with “second memory cell”)
a second wiring adjacent to the first wiring and extending in the first direction, the second wiring being electrically coupled to the second storage portion;
(US12211544B2: claim 9, lines 8-10: “…second bit line adjacent to the first bit line and extending 45 in the first direction, the second bit line being electrically coupled to the second memory cell…”)
a second circuit configured to sense a voltage of the second wiring; (US12211544B2: claim 9, lines 11-12: “…second sense amplifier configured to sense a voltage of the second bit line…”)
a third storage portion; (US12211544B2: claim 9, line 13: storage portion associated with “third memory cell”)
a third wiring not adjacent to the second wiring and extending in the first direction, the third wiring being electrically coupled to the third storage portion; and
(US12211544B2: claim 9, lines 14-16: “…third bit line not adjacent to the second bit line, the third bit line extending in the first direction and being electrically coupled to the third memory cell…”)
a third circuit configured to sense a voltage of the third wiring, (US12211544B2: claim 9, lines 17-18: “…third sense amplifier configured to sense a voltage of the third bit line…”)
wherein:
the first circuit and the second circuit belong to a first group, are adjacent to each other, and are arranged in a second direction intersecting the first direction,
(US12211544B2: claim 9, lines 20-23: “…first sense amplifier and the second sense amplifier belong to a first sense amplifier group, are adjacent to each other, and are arranged in a second direction intersecting to the first direction…”)
the third circuit belongs to a second group, the first group and the second group are adjacent to each other and arranged in the first direction, and
(US12211544B2: claim 9, lines 24-28: third sense amplifier belongs to a second sense amplifier group, the first sense amplifier group and the second sense amplifier group are adjacent to each other and arranged in the first direction…”)
the first circuit, the second circuit, and the third circuit extend in the first direction. (US12211544B2: claim 9, lines 29-30: “…first sense amplifier, the second sense amplifier, and the third sense amplifier extend in the first direction…”)
Regarding claim 6, US12211544B2 teaches the semiconductor device according to claim 1, wherein a first length of each of the first circuit, the second circuit, and the third circuit along the first direction is longer than a second length of each of the first circuit, the second circuit, and the third circuit along the second direction. (US12211544B2: claim 5, lines 1-6; and see also claim 9)
Regarding claim 7, US12211544B2 teaches the semiconductor device according to claim 1, wherein the first wiring, the second wiring, and the third wiring are disposed between the first, the second, and the third storage portions and the first, the second, and the third circuits in a fourth direction orthogonal to a surface of the substrate. (US12211544B2: claim 6, lines 1-5 and see also claim 9)
Regarding claim 8, US12211544B2 teaches the semiconductor device according to claim 1, further comprising: a plurality of conductive layers stacked above
the substrate in a fourth direction orthogonal to the first direction and the second direction; and a pillar extending in the fourth direction,
(US12211544B2: claim 7, lines 1-8 and see also claim 9)
the pillar passing through the plurality of conductive layers, and the pillar being electrically coupled to the first wiring. (US12211544B2: claim 7, lines 1-8 and see also claim 9)
Regarding claim 9, US12211544B2 teaches the semiconductor device according to claim 8, wherein: the conductive layers include word lines, and an
intersection between one of the conductive layers and the pillar functions as the first storage portion.
(US12211544B2: claim 8, lines 1-4 and see also claim 9)
Regarding independent claim 10, US12211544B2 teaches a semiconductor device (US12211544B2: claim 10, line 1) comprising:
a first wiring extending in a first direction; (US12211544B2: claim 10, line 2: “…first bit line extending in a first direction…”)
a second wiring adjacent to the first wiring, the second wiring extending in the first direction; (US12211544B2: claim 10, lines 3-4: “…second bit line adjacent to the first bit line, the second bit line extending in the first direction…”)
a third wiring extending in the first direction; (US12211544B2: claim 10, line 5: “…third bit line extending in the first direction…”)
a fourth wiring adjacent to the third wiring, the fourth wiring extending in the first direction; (US12211544B2: claim 10, lines 6-7: “…fourth bit line adjacent to the third bit line, the fourth bit line extending in the first direction…”)
a first group including: a first circuit configured to sense a voltage of the first wiring; and
(US12211544B2: claim 10, lines 8-10: “…first sense amplifier group including: a first sense amplifier configured to sense a voltage of the first bit line…”)
a second circuit configured to sense a voltage of the second wiring, (US12211544B2: claim 10, lines 11-12: “…second sense amplifier configured to sense a voltage of the second bit line…”)
the first circuit and the second circuit being arranged in a second direction intersecting the first direction; and
(US12211544B2: claim 10, lines 12-14: “…first sense amplifier and the second sense amplifier being arranged in a second direction intersecting the first direction…”)
a second group disposed adjacent to the first group in the first direction,
(US12211544B2: claim 10, lines 15-16: “…second sense amplifier group disposed adjacent to the first sense amplifier group in the first direction…”)
the second group including: a third circuit configured to sense a voltage of the third wiring; and
(US12211544B2: claim 10, lines 17-19: “…second sense amplifier group including: a third sense amplifier configured to sense a voltage of the third bit line…”)
a fourth circuit configured to sense a voltage of the fourth wiring, the third circuit and the fourth circuit being arranged in the second direction,
(US12211544B2: claim 10, lines 20-23: “…fourth sense amplifier configured to sense a voltage of the fourth bit line, the third sense amplifier and the fourth sense amplifier being arranged in the second direction…”)
a first pad disposed between the first wiring and the first circuit; a second pad disposed between the second wiring and the second circuit; a third pad disposed between the third wiring and the third circuit; and a fourth pad disposed between the fourth wiring and the fourth circuit, (US12211544B2: claim 10, lines 24-31: “…first pad disposed between the first bit line and the first sense amplifier; a second pad disposed between the second bit line and the second sense amplifier; a third pad disposed between the third bit line and the third sense amplifier; and a fourth pad disposed between the fourth bit line and the fourth sense amplifier…”)
wherein:
the first pad and the second pad are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction, and (US12211544B2: claim 10, lines 33-35: “…first pad and the second pad are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction…”)
the third pad and the fourth pad are adjacent to each other and are arranged in the first direction or the third direction. (US12211544B2: claim 10, lines 37-39: “…the third pad and the fourth pad are adjacent to each other and are arranged in the first direction or the third direction…”)
Regarding claim 11, US12211544B2 teaches the semiconductor device according to claim 10, further comprising: a first conductive layer; a fifth circuit coupled to the first conductive layer, the fifth circuit being configured to apply a first voltage to the first conductive layer; (US12211544B2: claim 11, lines 1-13):
a second conductive layer; and a sixth circuit coupled to the second conductive layer, the sixth circuit being configured to apply a second voltage to the second conductive layer, wherein the first group is disposed between the fifth circuit and the sixth circuit. (US12211544B2: claim 11, lines 1-13):
Regarding claim 12, US12211544B2 teaches the semiconductor device according to claim 10, further comprising: a first conductive line electrically coupled between the first pad and the first circuit, the first conductive line extending in the second direction; a second conductive line electrically coupled between the second pad and the second circuit, the second conductive line extending in the second direction; a third conductive line electrically coupled between the third pad and the third circuit, the third conductive line extending in the second direction; and a fourth conductive line electrically coupled between the fourth pad and the fourth circuit, the fourth conductive line extending in the second direction. (US12211544B2: claim 12, lines 1-14)
Regarding claim 13, US12211544B2 teaches the semiconductor device according to claim 12, wherein: the second conductive line extends in the second direction over the first circuit, and the fourth conductive line extends in the second direction over the third circuit. (US12211544B2: claim 13, lines 1-15)
Regarding claim 14, US12211544B2 teaches the semiconductor device according to claim 10, wherein the first circuit, the second circuit, the third circuit, and the fourth circuit extend in the first direction. (US12211544B2: claim 14, lines 1-4)
Regarding claim 15, US12211544B2 teaches the semiconductor device according to claim 10, wherein a first length of each of the first circuit, the second circuit, the third circuit, and the fourth circuit along the first direction is longer than a second length of each of the first circuit, the second circuit, the third circuit, and the fourth circuit along the second direction. (US12211544B2: claim 15, lines 1-7)
Regarding claim 16, US12211544B2 teaches the semiconductor device according to claim 10, wherein the first wiring, the second wiring, the third wiring, and the fourth wiring are disposed between the first, the second, the third and the fourth storage portions and the first, the second, the third and the fourth circuits in a fourth direction orthogonal to a surface of the substrate. (US12211544B2: claim 16, lines 1-6)
Regarding claim 17, US12211544B2 teaches the semiconductor device according to claim 10, further comprising: a plurality of conductive layers stacked above the substrate in a fourth direction orthogonal to the first direction and the second direction; and a pillar extending in the fourth direction, the pillar passing through the plurality of conductive layers, and the pillar being electrically coupled to the first wiring. (US12211544B2: claim 17, lines 1-8)
Regarding claim 18, US12211544B2 teaches the semiconductor device according to claim 17, wherein: the conductive layers include word lines, and an intersection between one of the conductive layers and the pillar functions as the first storage portion. (US12211544B2: claim 18, lines 1-4)
Allowable Subject Matter
Claims 1-18 are objected to for being rejection under NSDP double patenting rejection, but would be allowable if the rejection is over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Yanagidaira (US 2019/0080772 A1) is applicable for all claims. Yanagidaira teaches a memory device (Fig. 1: 10 Nand flash memory. See Fig. 1-Fig. 32 for illustrated components and functionality) comprising: a first memory cell (memory cell in first string in AR1 coupled to Fig. 21: BL0. See e.g., Fig. 8 for MTs and strings) provided above a substrate (See Fig. 8: 50, Fig. 2);
a first bit line (Fig. 21: BL0) extending in a first direction (Fig. 21: Bit lines outside the SAU region extend in x-direction);
a first sense amplifier (Fig. 21: SAU0 in SAG0) configured to sense a voltage of the first bit line (Fig. 21: BL0);
a second memory cell (memory cell in second string in AR1 coupled to BL1. See e.g., Fig. 8 for MTs and strings) provided above the substrate (See Fig. 8: 50, Fig. 2);
a second bit line (Fig. 21: BL1) adjacent to the first bit line (Fig. 21: BL1) and extending in the first direction (Fig. 21: x-direction),
the second bit line electrically coupled to the second memory cell (See para [0223]-para [0224], para [0070]-para [0073])
a second sense amplifier (Fig. 21: SAU1 in SAG0) configured to sense a voltage of the second bit line (Fig. 21: BL1);
a third memory cell (memory cell in third string in AR1 coupled to BLb) provided above the substrate (See Fig. 8: 50, Fig. 2);
a third bit line (Fig. 21: BLb) not adjacent to the second bit line (Fig. 21: BLb): extending in the first direction (Fig. 21: x-direction), the third bit line electrically coupled to the third memory cell (See para [0223]-para [0224], para [0070]-para [0073]); and
a third sense amplifier (Fig. 21: SAU0 in SAG1) configured to sense a voltage of the third bit line (Fig. 21: BLb), wherein:
the first sense amplifier (Fig. 21: SAU0 in SAG0) and the second sense amplifier (Fig. 21: SAU1 in SAG0 belong to a first sense amplifier group (Fig. 21: SAG0),
are adjacent to each other and are arranged in a second direction intersecting to the first direction (Fig. 21: y-direction),
the third sense amplifier (Fig. 21: SAU0 in SAG1) belongs to a second sense amplifier group (Fig. 21: SAG1), and
the first sense amplifier group (Fig. 21: SAG0) and the second sense amplifier group (Fig. 21: SAG1) are adjacent to each other and arranged in the first direction
US 2020/0335513 A1: Fig. 1-Fig. 21 and associated disclosure applicable for all claims. MAEJIMA et al. (US 2020/0395341 A1) is applicable for all claims. MAEJIMA et al. teaches a semiconductor memory device (Fig. 1: 1 “semiconductor memory device”, see Fig. 1-Fig. 18 for illustrated circuitry structures and functions. See Examiner’s Markup of Figure 8 top layout view) comprising: a first memory cell (Fig. 8: MP1) provided above a substrate (Fig. 6: MEMORY CHIP MC above substrate, see para [0078]); a first bit line (Fig. 8: BL1) extending in a first direction (Fig. 6-8: y-direction), the first bit line being electrically coupled to the first memory cell (Fig. 8, Fig. 9: coupled to MP1 via CV); a first pad (Fig. 8: see BP1 which overlaps with CV. See Fig. 9: BP and CV overlap and see Fig. 6: BP) electrically coupled to the first bit line (Fig. 8: BL1, see Fig. 9: BL); a first sense amplifier (Fig. 3: SAU0 in Fig. 6: SR region, See in context of Fig. 3, Fig. 6, Fig. Fig. 14) electrically coupled to the first pad (Fig. 8: BP1 vias BL1, see Fig. 9), the first sense amplifier being configured to sense a voltage of the first bit line (Fig. 3, Fig. 8 in context of para [0058]); a second memory cell (Fig. 8: MP2) provided above the substrate (Fig. 5: MEMORY CHIP MC above substrate, see para [0078]); a second bit line (Fig. 8: BL2) being adjacent to the first bit line (Fig. 8: BL1) and extending in the first direction (Fig. 6-8: y-direction), the second bit line being electrically coupled to the second memory cell (Fig. 8, Fig. 9: coupled to MP2 via CV); a second pad (Fig. 8: BP2 which overlaps with CV. See Fig. 9: BP, Fig. 6: BP) electrically coupled to the second bit line (Fig. 8: BL2); and a second sense amplifier (Fig. 3: SAU1 in Fig. 6: SR region, See in context of Fig. 3, Fig. 6, Fig. Fig. 14) electrically coupled to the second pad (Fig. 8: BP2 vias BL2, see Fig. 9), the second sense amplifier being configured to sense a voltage of the second bit line (Fig. 3, Fig. 8 in context of para [0058]), wherein the first sense amplifier (Fig. 3: SAU0 in Fig. 6: SR region) and the second sense amplifier (Fig. 3: SAU1 in Fig. 6: SR region) are adjacent to each other (Fig. 6: located in SR of CMOS CHIP CC) and are arranged in a second direction (Fig. 6-8: x-direction) intersecting the first direction (Fig. 6-8: y-direction), and the first pad (Fig. 8: BP1) and the second pad (Fig. 8: BP2) are adjacent to each other (see Fig. 8) and are arranged in a third direction (Diagonal direction, see Fig. 8 arrow) intersecting the first direction and the second direction (see Fig. 8).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
Prosecution Insights